#ifndef _RTL8367D_REG_H_
#define _RTL8367D_REG_H_

/************************************************************
auto-generated register address and field data
*************************************************************/

/* (16'h0000)port_reg */

#define    RTL8367D_REG_PORT0_CGST_HALF_CFG    0x0000
#define    RTL8367D_PORT0_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4
#define    RTL8367D_PORT0_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0
#define    RTL8367D_PORT0_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT0_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_PKTGEN_PORT0_TIMER    0x000d
#define    RTL8367D_PKTGEN_PORT0_TIMER_TIMER_OFFSET    4
#define    RTL8367D_PKTGEN_PORT0_TIMER_TIMER_MASK    0xF0
#define    RTL8367D_PKTGEN_PORT0_TIMER_RX_DMA_ERR_FLAG_OFFSET    3
#define    RTL8367D_PKTGEN_PORT0_TIMER_RX_DMA_ERR_FLAG_MASK    0x8

#define    RTL8367D_REG_PORT0_MISC_CFG    0x000e
#define    RTL8367D_PORT0_MISC_CFG_SMALL_TAG_IPG_OFFSET    15
#define    RTL8367D_PORT0_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000
#define    RTL8367D_PORT0_MISC_CFG_TX_ITFSP_MODE_OFFSET    14
#define    RTL8367D_PORT0_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000
#define    RTL8367D_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12
#define    RTL8367D_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000
#define    RTL8367D_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11
#define    RTL8367D_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800
#define    RTL8367D_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET    10
#define    RTL8367D_PORT0_MISC_CFG_INGRESSBW_IFG_MASK    0x400
#define    RTL8367D_PORT0_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8367D_PORT0_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8367D_PORT0_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8367D_PORT0_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8367D_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8367D_PORT0_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8367D_PORT0_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4
#define    RTL8367D_PORT0_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30
#define    RTL8367D_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_INGRESSBW_PORT0_RATE_CTRL0    0x000f

#define    RTL8367D_REG_INGRESSBW_PORT0_RATE_CTRL1    0x0010
#define    RTL8367D_INGRESSBW_PORT0_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET    3
#define    RTL8367D_INGRESSBW_PORT0_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK    0x8
#define    RTL8367D_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0
#define    RTL8367D_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7

#define    RTL8367D_REG_PORT0_FORCE_RATE0    0x0011

#define    RTL8367D_REG_PORT0_FORCE_RATE1    0x0012

#define    RTL8367D_REG_PORT0_CURENT_RATE0    0x0013

#define    RTL8367D_REG_PORT0_CURENT_RATE1    0x0014

#define    RTL8367D_REG_PORT0_PAGE_COUNTER    0x0015
#define    RTL8367D_PORT0_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_PORT0_PAGE_COUNTER_MASK    0x7F

#define    RTL8367D_REG_PAGEMETER_PORT0_CTRL0    0x0016

#define    RTL8367D_REG_PAGEMETER_PORT0_CTRL1    0x0017

#define    RTL8367D_REG_PORT0_EEECFG    0x0018
#define    RTL8367D_PORT0_EEECFG_EEE_PORT_TX_EN_OFFSET    9
#define    RTL8367D_PORT0_EEECFG_EEE_PORT_TX_EN_MASK    0x200
#define    RTL8367D_PORT0_EEECFG_EEE_PORT_RX_EN_OFFSET    8
#define    RTL8367D_PORT0_EEECFG_EEE_PORT_RX_EN_MASK    0x100
#define    RTL8367D_PORT0_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8367D_PORT0_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8367D_PORT0_EEECFG_EEE_TX_STS_OFFSET    4
#define    RTL8367D_PORT0_EEECFG_EEE_TX_STS_MASK    0x10
#define    RTL8367D_PORT0_EEECFG_EEE_RX_STS_OFFSET    3
#define    RTL8367D_PORT0_EEECFG_EEE_RX_STS_MASK    0x8
#define    RTL8367D_PORT0_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8367D_PORT0_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4

#define    RTL8367D_REG_PORT0_EEETXMTR    0x0019

#define    RTL8367D_REG_PORT0_EEERXMTR    0x001a

#define    RTL8367D_REG_PORT0_DUMMY    0x001e

#define    RTL8367D_REG_P0_MSIC1    0x001f
#define    RTL8367D_P0_MSIC1_OFFSET    0
#define    RTL8367D_P0_MSIC1_MASK    0x1

#define    RTL8367D_REG_PORT1_CGST_HALF_CFG    0x0020
#define    RTL8367D_PORT1_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4
#define    RTL8367D_PORT1_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0
#define    RTL8367D_PORT1_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT1_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_PKTGEN_PORT1_TIMER    0x002d
#define    RTL8367D_PKTGEN_PORT1_TIMER_TIMER_OFFSET    4
#define    RTL8367D_PKTGEN_PORT1_TIMER_TIMER_MASK    0xF0
#define    RTL8367D_PKTGEN_PORT1_TIMER_RX_DMA_ERR_FLAG_OFFSET    3
#define    RTL8367D_PKTGEN_PORT1_TIMER_RX_DMA_ERR_FLAG_MASK    0x8

#define    RTL8367D_REG_PORT1_MISC_CFG    0x002e
#define    RTL8367D_PORT1_MISC_CFG_SMALL_TAG_IPG_OFFSET    15
#define    RTL8367D_PORT1_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000
#define    RTL8367D_PORT1_MISC_CFG_TX_ITFSP_MODE_OFFSET    14
#define    RTL8367D_PORT1_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000
#define    RTL8367D_PORT1_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12
#define    RTL8367D_PORT1_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000
#define    RTL8367D_PORT1_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11
#define    RTL8367D_PORT1_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800
#define    RTL8367D_PORT1_MISC_CFG_INGRESSBW_IFG_OFFSET    10
#define    RTL8367D_PORT1_MISC_CFG_INGRESSBW_IFG_MASK    0x400
#define    RTL8367D_PORT1_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8367D_PORT1_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8367D_PORT1_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8367D_PORT1_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8367D_PORT1_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8367D_PORT1_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8367D_PORT1_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4
#define    RTL8367D_PORT1_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30
#define    RTL8367D_PORT1_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT1_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_INGRESSBW_PORT1_RATE_CTRL0    0x002f

#define    RTL8367D_REG_INGRESSBW_PORT1_RATE_CTRL1    0x0030
#define    RTL8367D_INGRESSBW_PORT1_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET    3
#define    RTL8367D_INGRESSBW_PORT1_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK    0x8
#define    RTL8367D_INGRESSBW_PORT1_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0
#define    RTL8367D_INGRESSBW_PORT1_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7

#define    RTL8367D_REG_PORT1_FORCE_RATE0    0x0031

#define    RTL8367D_REG_PORT1_FORCE_RATE1    0x0032

#define    RTL8367D_REG_PORT1_CURENT_RATE0    0x0033

#define    RTL8367D_REG_PORT1_CURENT_RATE1    0x0034

#define    RTL8367D_REG_PORT1_PAGE_COUNTER    0x0035
#define    RTL8367D_PORT1_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_PORT1_PAGE_COUNTER_MASK    0x7F

#define    RTL8367D_REG_PAGEMETER_PORT1_CTRL0    0x0036

#define    RTL8367D_REG_PAGEMETER_PORT1_CTRL1    0x0037

#define    RTL8367D_REG_PORT1_EEECFG    0x0038
#define    RTL8367D_PORT1_EEECFG_EEE_PORT_TX_EN_OFFSET    9
#define    RTL8367D_PORT1_EEECFG_EEE_PORT_TX_EN_MASK    0x200
#define    RTL8367D_PORT1_EEECFG_EEE_PORT_RX_EN_OFFSET    8
#define    RTL8367D_PORT1_EEECFG_EEE_PORT_RX_EN_MASK    0x100
#define    RTL8367D_PORT1_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8367D_PORT1_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8367D_PORT1_EEECFG_EEE_TX_STS_OFFSET    4
#define    RTL8367D_PORT1_EEECFG_EEE_TX_STS_MASK    0x10
#define    RTL8367D_PORT1_EEECFG_EEE_RX_STS_OFFSET    3
#define    RTL8367D_PORT1_EEECFG_EEE_RX_STS_MASK    0x8
#define    RTL8367D_PORT1_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8367D_PORT1_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4

#define    RTL8367D_REG_PORT1_EEETXMTR    0x0039

#define    RTL8367D_REG_PORT1_EEERXMTR    0x003a

#define    RTL8367D_REG_PORT1_DUMMY    0x003e

#define    RTL8367D_REG_P1_MSIC1    0x003f
#define    RTL8367D_P1_MSIC1_OFFSET    0
#define    RTL8367D_P1_MSIC1_MASK    0x1

#define    RTL8367D_REG_PORT2_CGST_HALF_CFG    0x0040
#define    RTL8367D_PORT2_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4
#define    RTL8367D_PORT2_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0
#define    RTL8367D_PORT2_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT2_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_PKTGEN_PORT2_TIMER    0x004d
#define    RTL8367D_PKTGEN_PORT2_TIMER_TIMER_OFFSET    4
#define    RTL8367D_PKTGEN_PORT2_TIMER_TIMER_MASK    0xF0
#define    RTL8367D_PKTGEN_PORT2_TIMER_RX_DMA_ERR_FLAG_OFFSET    3
#define    RTL8367D_PKTGEN_PORT2_TIMER_RX_DMA_ERR_FLAG_MASK    0x8

#define    RTL8367D_REG_PORT2_MISC_CFG    0x004e
#define    RTL8367D_PORT2_MISC_CFG_SMALL_TAG_IPG_OFFSET    15
#define    RTL8367D_PORT2_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000
#define    RTL8367D_PORT2_MISC_CFG_TX_ITFSP_MODE_OFFSET    14
#define    RTL8367D_PORT2_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000
#define    RTL8367D_PORT2_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12
#define    RTL8367D_PORT2_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000
#define    RTL8367D_PORT2_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11
#define    RTL8367D_PORT2_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800
#define    RTL8367D_PORT2_MISC_CFG_INGRESSBW_IFG_OFFSET    10
#define    RTL8367D_PORT2_MISC_CFG_INGRESSBW_IFG_MASK    0x400
#define    RTL8367D_PORT2_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8367D_PORT2_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8367D_PORT2_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8367D_PORT2_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8367D_PORT2_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8367D_PORT2_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8367D_PORT2_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4
#define    RTL8367D_PORT2_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30
#define    RTL8367D_PORT2_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT2_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_INGRESSBW_PORT2_RATE_CTRL0    0x004f

#define    RTL8367D_REG_INGRESSBW_PORT2_RATE_CTRL1    0x0050
#define    RTL8367D_INGRESSBW_PORT2_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET    3
#define    RTL8367D_INGRESSBW_PORT2_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK    0x8
#define    RTL8367D_INGRESSBW_PORT2_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0
#define    RTL8367D_INGRESSBW_PORT2_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7

#define    RTL8367D_REG_PORT2_FORCE_RATE0    0x0051

#define    RTL8367D_REG_PORT2_FORCE_RATE1    0x0052

#define    RTL8367D_REG_PORT2_CURENT_RATE0    0x0053

#define    RTL8367D_REG_PORT2_CURENT_RATE1    0x0054

#define    RTL8367D_REG_PORT2_PAGE_COUNTER    0x0055
#define    RTL8367D_PORT2_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_PORT2_PAGE_COUNTER_MASK    0x7F

#define    RTL8367D_REG_PAGEMETER_PORT2_CTRL0    0x0056

#define    RTL8367D_REG_PAGEMETER_PORT2_CTRL1    0x0057

#define    RTL8367D_REG_PORT2_EEECFG    0x0058
#define    RTL8367D_PORT2_EEECFG_EEE_PORT_TX_EN_OFFSET    9
#define    RTL8367D_PORT2_EEECFG_EEE_PORT_TX_EN_MASK    0x200
#define    RTL8367D_PORT2_EEECFG_EEE_PORT_RX_EN_OFFSET    8
#define    RTL8367D_PORT2_EEECFG_EEE_PORT_RX_EN_MASK    0x100
#define    RTL8367D_PORT2_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8367D_PORT2_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8367D_PORT2_EEECFG_EEE_TX_STS_OFFSET    4
#define    RTL8367D_PORT2_EEECFG_EEE_TX_STS_MASK    0x10
#define    RTL8367D_PORT2_EEECFG_EEE_RX_STS_OFFSET    3
#define    RTL8367D_PORT2_EEECFG_EEE_RX_STS_MASK    0x8
#define    RTL8367D_PORT2_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8367D_PORT2_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4

#define    RTL8367D_REG_PORT2_EEETXMTR    0x0059

#define    RTL8367D_REG_PORT2_EEERXMTR    0x005a

#define    RTL8367D_REG_PORT2_DUMMY    0x005e

#define    RTL8367D_REG_P2_MSIC1    0x005f
#define    RTL8367D_P2_MSIC1_OFFSET    0
#define    RTL8367D_P2_MSIC1_MASK    0x1

#define    RTL8367D_REG_PORT3_CGST_HALF_CFG    0x0060
#define    RTL8367D_PORT3_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4
#define    RTL8367D_PORT3_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0
#define    RTL8367D_PORT3_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT3_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_PKTGEN_PORT3_TIMER    0x006d
#define    RTL8367D_PKTGEN_PORT3_TIMER_TIMER_OFFSET    4
#define    RTL8367D_PKTGEN_PORT3_TIMER_TIMER_MASK    0xF0
#define    RTL8367D_PKTGEN_PORT3_TIMER_RX_DMA_ERR_FLAG_OFFSET    3
#define    RTL8367D_PKTGEN_PORT3_TIMER_RX_DMA_ERR_FLAG_MASK    0x8

#define    RTL8367D_REG_PORT3_MISC_CFG    0x006e
#define    RTL8367D_PORT3_MISC_CFG_SMALL_TAG_IPG_OFFSET    15
#define    RTL8367D_PORT3_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000
#define    RTL8367D_PORT3_MISC_CFG_TX_ITFSP_MODE_OFFSET    14
#define    RTL8367D_PORT3_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000
#define    RTL8367D_PORT3_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12
#define    RTL8367D_PORT3_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000
#define    RTL8367D_PORT3_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11
#define    RTL8367D_PORT3_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800
#define    RTL8367D_PORT3_MISC_CFG_INGRESSBW_IFG_OFFSET    10
#define    RTL8367D_PORT3_MISC_CFG_INGRESSBW_IFG_MASK    0x400
#define    RTL8367D_PORT3_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8367D_PORT3_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8367D_PORT3_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8367D_PORT3_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8367D_PORT3_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8367D_PORT3_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8367D_PORT3_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4
#define    RTL8367D_PORT3_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30
#define    RTL8367D_PORT3_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT3_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_INGRESSBW_PORT3_RATE_CTRL0    0x006f

#define    RTL8367D_REG_INGRESSBW_PORT3_RATE_CTRL1    0x0070
#define    RTL8367D_INGRESSBW_PORT3_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET    3
#define    RTL8367D_INGRESSBW_PORT3_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK    0x8
#define    RTL8367D_INGRESSBW_PORT3_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0
#define    RTL8367D_INGRESSBW_PORT3_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7

#define    RTL8367D_REG_PORT3_FORCE_RATE0    0x0071

#define    RTL8367D_REG_PORT3_FORCE_RATE1    0x0072

#define    RTL8367D_REG_PORT3_CURENT_RATE0    0x0073

#define    RTL8367D_REG_PORT3_CURENT_RATE1    0x0074

#define    RTL8367D_REG_PORT3_PAGE_COUNTER    0x0075
#define    RTL8367D_PORT3_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_PORT3_PAGE_COUNTER_MASK    0x7F

#define    RTL8367D_REG_PAGEMETER_PORT3_CTRL0    0x0076

#define    RTL8367D_REG_PAGEMETER_PORT3_CTRL1    0x0077

#define    RTL8367D_REG_PORT3_EEECFG    0x0078
#define    RTL8367D_PORT3_EEECFG_EEE_PORT_TX_EN_OFFSET    9
#define    RTL8367D_PORT3_EEECFG_EEE_PORT_TX_EN_MASK    0x200
#define    RTL8367D_PORT3_EEECFG_EEE_PORT_RX_EN_OFFSET    8
#define    RTL8367D_PORT3_EEECFG_EEE_PORT_RX_EN_MASK    0x100
#define    RTL8367D_PORT3_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8367D_PORT3_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8367D_PORT3_EEECFG_EEE_TX_STS_OFFSET    4
#define    RTL8367D_PORT3_EEECFG_EEE_TX_STS_MASK    0x10
#define    RTL8367D_PORT3_EEECFG_EEE_RX_STS_OFFSET    3
#define    RTL8367D_PORT3_EEECFG_EEE_RX_STS_MASK    0x8
#define    RTL8367D_PORT3_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8367D_PORT3_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4

#define    RTL8367D_REG_PORT3_EEETXMTR    0x0079

#define    RTL8367D_REG_PORT3_EEERXMTR    0x007a

#define    RTL8367D_REG_PORT3_DUMMY    0x007e

#define    RTL8367D_REG_P3_MSIC1    0x007f
#define    RTL8367D_P3_MSIC1_OFFSET    0
#define    RTL8367D_P3_MSIC1_MASK    0x1

#define    RTL8367D_REG_PORT4_CGST_HALF_CFG    0x0080
#define    RTL8367D_PORT4_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4
#define    RTL8367D_PORT4_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0
#define    RTL8367D_PORT4_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT4_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_PKTGEN_PORT4_TIMER    0x008d
#define    RTL8367D_PKTGEN_PORT4_TIMER_TIMER_OFFSET    4
#define    RTL8367D_PKTGEN_PORT4_TIMER_TIMER_MASK    0xF0
#define    RTL8367D_PKTGEN_PORT4_TIMER_RX_DMA_ERR_FLAG_OFFSET    3
#define    RTL8367D_PKTGEN_PORT4_TIMER_RX_DMA_ERR_FLAG_MASK    0x8

#define    RTL8367D_REG_PORT4_MISC_CFG    0x008e
#define    RTL8367D_PORT4_MISC_CFG_SMALL_TAG_IPG_OFFSET    15
#define    RTL8367D_PORT4_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000
#define    RTL8367D_PORT4_MISC_CFG_TX_ITFSP_MODE_OFFSET    14
#define    RTL8367D_PORT4_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000
#define    RTL8367D_PORT4_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12
#define    RTL8367D_PORT4_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000
#define    RTL8367D_PORT4_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11
#define    RTL8367D_PORT4_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800
#define    RTL8367D_PORT4_MISC_CFG_INGRESSBW_IFG_OFFSET    10
#define    RTL8367D_PORT4_MISC_CFG_INGRESSBW_IFG_MASK    0x400
#define    RTL8367D_PORT4_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8367D_PORT4_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8367D_PORT4_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8367D_PORT4_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8367D_PORT4_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8367D_PORT4_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8367D_PORT4_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4
#define    RTL8367D_PORT4_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30
#define    RTL8367D_PORT4_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT4_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_INGRESSBW_PORT4_RATE_CTRL0    0x008f

#define    RTL8367D_REG_INGRESSBW_PORT4_RATE_CTRL1    0x0090
#define    RTL8367D_INGRESSBW_PORT4_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET    3
#define    RTL8367D_INGRESSBW_PORT4_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK    0x8
#define    RTL8367D_INGRESSBW_PORT4_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0
#define    RTL8367D_INGRESSBW_PORT4_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7

#define    RTL8367D_REG_PORT4_FORCE_RATE0    0x0091

#define    RTL8367D_REG_PORT4_FORCE_RATE1    0x0092

#define    RTL8367D_REG_PORT4_CURENT_RATE0    0x0093

#define    RTL8367D_REG_PORT4_CURENT_RATE1    0x0094

#define    RTL8367D_REG_PORT4_PAGE_COUNTER    0x0095
#define    RTL8367D_PORT4_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_PORT4_PAGE_COUNTER_MASK    0x7F

#define    RTL8367D_REG_PAGEMETER_PORT4_CTRL0    0x0096

#define    RTL8367D_REG_PAGEMETER_PORT4_CTRL1    0x0097

#define    RTL8367D_REG_PORT4_EEECFG    0x0098
#define    RTL8367D_PORT4_EEECFG_EEE_PORT_TX_EN_OFFSET    9
#define    RTL8367D_PORT4_EEECFG_EEE_PORT_TX_EN_MASK    0x200
#define    RTL8367D_PORT4_EEECFG_EEE_PORT_RX_EN_OFFSET    8
#define    RTL8367D_PORT4_EEECFG_EEE_PORT_RX_EN_MASK    0x100
#define    RTL8367D_PORT4_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8367D_PORT4_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8367D_PORT4_EEECFG_EEE_TX_STS_OFFSET    4
#define    RTL8367D_PORT4_EEECFG_EEE_TX_STS_MASK    0x10
#define    RTL8367D_PORT4_EEECFG_EEE_RX_STS_OFFSET    3
#define    RTL8367D_PORT4_EEECFG_EEE_RX_STS_MASK    0x8
#define    RTL8367D_PORT4_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8367D_PORT4_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4

#define    RTL8367D_REG_PORT4_EEETXMTR    0x0099

#define    RTL8367D_REG_PORT4_EEERXMTR    0x009a

#define    RTL8367D_REG_PORT4_DUMMY    0x009e

#define    RTL8367D_REG_P4_MSIC1    0x009f
#define    RTL8367D_P4_MSIC1_OFFSET    0
#define    RTL8367D_P4_MSIC1_MASK    0x1

#define    RTL8367D_REG_PORT5_CGST_HALF_CFG    0x00a0
#define    RTL8367D_PORT5_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4
#define    RTL8367D_PORT5_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0
#define    RTL8367D_PORT5_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT5_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_PKTGEN_PORT5_TIMER    0x00ad
#define    RTL8367D_PKTGEN_PORT5_TIMER_TIMER_OFFSET    4
#define    RTL8367D_PKTGEN_PORT5_TIMER_TIMER_MASK    0xF0
#define    RTL8367D_PKTGEN_PORT5_TIMER_RX_DMA_ERR_FLAG_OFFSET    3
#define    RTL8367D_PKTGEN_PORT5_TIMER_RX_DMA_ERR_FLAG_MASK    0x8

#define    RTL8367D_REG_PORT5_MISC_CFG    0x00ae
#define    RTL8367D_PORT5_MISC_CFG_SMALL_TAG_IPG_OFFSET    15
#define    RTL8367D_PORT5_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000
#define    RTL8367D_PORT5_MISC_CFG_TX_ITFSP_MODE_OFFSET    14
#define    RTL8367D_PORT5_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000
#define    RTL8367D_PORT5_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12
#define    RTL8367D_PORT5_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000
#define    RTL8367D_PORT5_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11
#define    RTL8367D_PORT5_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800
#define    RTL8367D_PORT5_MISC_CFG_INGRESSBW_IFG_OFFSET    10
#define    RTL8367D_PORT5_MISC_CFG_INGRESSBW_IFG_MASK    0x400
#define    RTL8367D_PORT5_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8367D_PORT5_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8367D_PORT5_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8367D_PORT5_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8367D_PORT5_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8367D_PORT5_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8367D_PORT5_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4
#define    RTL8367D_PORT5_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30
#define    RTL8367D_PORT5_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT5_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_INGRESSBW_PORT5_RATE_CTRL0    0x00af

#define    RTL8367D_REG_INGRESSBW_PORT5_RATE_CTRL1    0x00b0
#define    RTL8367D_INGRESSBW_PORT5_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET    3
#define    RTL8367D_INGRESSBW_PORT5_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK    0x8
#define    RTL8367D_INGRESSBW_PORT5_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0
#define    RTL8367D_INGRESSBW_PORT5_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7

#define    RTL8367D_REG_PORT5_FORCE_RATE0    0x00b1

#define    RTL8367D_REG_PORT5_FORCE_RATE1    0x00b2

#define    RTL8367D_REG_PORT5_CURENT_RATE0    0x00b3

#define    RTL8367D_REG_PORT5_CURENT_RATE1    0x00b4

#define    RTL8367D_REG_PORT5_PAGE_COUNTER    0x00b5
#define    RTL8367D_PORT5_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_PORT5_PAGE_COUNTER_MASK    0x7F

#define    RTL8367D_REG_PAGEMETER_PORT5_CTRL0    0x00b6

#define    RTL8367D_REG_PAGEMETER_PORT5_CTRL1    0x00b7

#define    RTL8367D_REG_PORT5_EEECFG    0x00b8
#define    RTL8367D_PORT5_EEECFG_EEE_PORT_TX_EN_OFFSET    9
#define    RTL8367D_PORT5_EEECFG_EEE_PORT_TX_EN_MASK    0x200
#define    RTL8367D_PORT5_EEECFG_EEE_PORT_RX_EN_OFFSET    8
#define    RTL8367D_PORT5_EEECFG_EEE_PORT_RX_EN_MASK    0x100
#define    RTL8367D_PORT5_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8367D_PORT5_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8367D_PORT5_EEECFG_EEE_TX_STS_OFFSET    4
#define    RTL8367D_PORT5_EEECFG_EEE_TX_STS_MASK    0x10
#define    RTL8367D_PORT5_EEECFG_EEE_RX_STS_OFFSET    3
#define    RTL8367D_PORT5_EEECFG_EEE_RX_STS_MASK    0x8
#define    RTL8367D_PORT5_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8367D_PORT5_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4

#define    RTL8367D_REG_PORT5_EEETXMTR    0x00b9

#define    RTL8367D_REG_PORT5_EEERXMTR    0x00ba

#define    RTL8367D_REG_PORT5_DUMMY    0x00be

#define    RTL8367D_REG_P5_MSIC1    0x00bf
#define    RTL8367D_P5_MSIC1_OFFSET    0
#define    RTL8367D_P5_MSIC1_MASK    0x1

#define    RTL8367D_REG_PORT6_CGST_HALF_CFG    0x00c0
#define    RTL8367D_PORT6_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4
#define    RTL8367D_PORT6_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0
#define    RTL8367D_PORT6_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT6_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_PKTGEN_PORT6_TIMER    0x00cd
#define    RTL8367D_PKTGEN_PORT6_TIMER_TIMER_OFFSET    4
#define    RTL8367D_PKTGEN_PORT6_TIMER_TIMER_MASK    0xF0
#define    RTL8367D_PKTGEN_PORT6_TIMER_RX_DMA_ERR_FLAG_OFFSET    3
#define    RTL8367D_PKTGEN_PORT6_TIMER_RX_DMA_ERR_FLAG_MASK    0x8

#define    RTL8367D_REG_PORT6_MISC_CFG    0x00ce
#define    RTL8367D_PORT6_MISC_CFG_SMALL_TAG_IPG_OFFSET    15
#define    RTL8367D_PORT6_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000
#define    RTL8367D_PORT6_MISC_CFG_TX_ITFSP_MODE_OFFSET    14
#define    RTL8367D_PORT6_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000
#define    RTL8367D_PORT6_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12
#define    RTL8367D_PORT6_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000
#define    RTL8367D_PORT6_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11
#define    RTL8367D_PORT6_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800
#define    RTL8367D_PORT6_MISC_CFG_INGRESSBW_IFG_OFFSET    10
#define    RTL8367D_PORT6_MISC_CFG_INGRESSBW_IFG_MASK    0x400
#define    RTL8367D_PORT6_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8367D_PORT6_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8367D_PORT6_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8367D_PORT6_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8367D_PORT6_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8367D_PORT6_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8367D_PORT6_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4
#define    RTL8367D_PORT6_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30
#define    RTL8367D_PORT6_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT6_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_INGRESSBW_PORT6_RATE_CTRL0    0x00cf

#define    RTL8367D_REG_INGRESSBW_PORT6_RATE_CTRL1    0x00d0
#define    RTL8367D_INGRESSBW_PORT6_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET    3
#define    RTL8367D_INGRESSBW_PORT6_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK    0x8
#define    RTL8367D_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0
#define    RTL8367D_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7

#define    RTL8367D_REG_PORT6_FORCE_RATE0    0x00d1

#define    RTL8367D_REG_PORT6_FORCE_RATE1    0x00d2

#define    RTL8367D_REG_PORT6_CURENT_RATE0    0x00d3

#define    RTL8367D_REG_PORT6_CURENT_RATE1    0x00d4

#define    RTL8367D_REG_PORT6_PAGE_COUNTER    0x00d5
#define    RTL8367D_PORT6_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_PORT6_PAGE_COUNTER_MASK    0x7F

#define    RTL8367D_REG_PAGEMETER_PORT6_CTRL0    0x00d6

#define    RTL8367D_REG_PAGEMETER_PORT6_CTRL1    0x00d7

#define    RTL8367D_REG_PORT6_EEECFG    0x00d8
#define    RTL8367D_PORT6_EEECFG_EEE_PORT_TX_EN_OFFSET    9
#define    RTL8367D_PORT6_EEECFG_EEE_PORT_TX_EN_MASK    0x200
#define    RTL8367D_PORT6_EEECFG_EEE_PORT_RX_EN_OFFSET    8
#define    RTL8367D_PORT6_EEECFG_EEE_PORT_RX_EN_MASK    0x100
#define    RTL8367D_PORT6_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8367D_PORT6_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8367D_PORT6_EEECFG_EEE_TX_STS_OFFSET    4
#define    RTL8367D_PORT6_EEECFG_EEE_TX_STS_MASK    0x10
#define    RTL8367D_PORT6_EEECFG_EEE_RX_STS_OFFSET    3
#define    RTL8367D_PORT6_EEECFG_EEE_RX_STS_MASK    0x8
#define    RTL8367D_PORT6_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8367D_PORT6_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4

#define    RTL8367D_REG_PORT6_EEETXMTR    0x00d9

#define    RTL8367D_REG_PORT6_EEERXMTR    0x00da

#define    RTL8367D_REG_PORT6_DUMMY    0x00de

#define    RTL8367D_REG_P6_MSIC1    0x00df
#define    RTL8367D_P6_MSIC1_OFFSET    0
#define    RTL8367D_P6_MSIC1_MASK    0x1

#define    RTL8367D_REG_PORT7_CGST_HALF_CFG    0x00e0
#define    RTL8367D_PORT7_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4
#define    RTL8367D_PORT7_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0
#define    RTL8367D_PORT7_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT7_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_PKTGEN_PORT7_TIMER    0x00ed
#define    RTL8367D_PKTGEN_PORT7_TIMER_TIMER_OFFSET    4
#define    RTL8367D_PKTGEN_PORT7_TIMER_TIMER_MASK    0xF0
#define    RTL8367D_PKTGEN_PORT7_TIMER_RX_DMA_ERR_FLAG_OFFSET    3
#define    RTL8367D_PKTGEN_PORT7_TIMER_RX_DMA_ERR_FLAG_MASK    0x8

#define    RTL8367D_REG_PORT7_MISC_CFG    0x00ee
#define    RTL8367D_PORT7_MISC_CFG_SMALL_TAG_IPG_OFFSET    15
#define    RTL8367D_PORT7_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000
#define    RTL8367D_PORT7_MISC_CFG_TX_ITFSP_MODE_OFFSET    14
#define    RTL8367D_PORT7_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000
#define    RTL8367D_PORT7_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12
#define    RTL8367D_PORT7_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000
#define    RTL8367D_PORT7_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11
#define    RTL8367D_PORT7_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800
#define    RTL8367D_PORT7_MISC_CFG_INGRESSBW_IFG_OFFSET    10
#define    RTL8367D_PORT7_MISC_CFG_INGRESSBW_IFG_MASK    0x400
#define    RTL8367D_PORT7_MISC_CFG_RX_SPC_OFFSET    9
#define    RTL8367D_PORT7_MISC_CFG_RX_SPC_MASK    0x200
#define    RTL8367D_PORT7_MISC_CFG_CRC_SKIP_OFFSET    8
#define    RTL8367D_PORT7_MISC_CFG_CRC_SKIP_MASK    0x100
#define    RTL8367D_PORT7_MISC_CFG_MAC_LOOPBACK_OFFSET    6
#define    RTL8367D_PORT7_MISC_CFG_MAC_LOOPBACK_MASK    0x40
#define    RTL8367D_PORT7_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4
#define    RTL8367D_PORT7_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30
#define    RTL8367D_PORT7_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0
#define    RTL8367D_PORT7_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF

#define    RTL8367D_REG_INGRESSBW_PORT7_RATE_CTRL0    0x00ef

#define    RTL8367D_REG_INGRESSBW_PORT7_RATE_CTRL1    0x00f0
#define    RTL8367D_INGRESSBW_PORT7_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET    3
#define    RTL8367D_INGRESSBW_PORT7_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK    0x8
#define    RTL8367D_INGRESSBW_PORT7_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0
#define    RTL8367D_INGRESSBW_PORT7_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7

#define    RTL8367D_REG_PORT7_FORCE_RATE0    0x00f1

#define    RTL8367D_REG_PORT7_FORCE_RATE1    0x00f2

#define    RTL8367D_REG_PORT7_CURENT_RATE0    0x00f3

#define    RTL8367D_REG_PORT7_CURENT_RATE1    0x00f4

#define    RTL8367D_REG_PORT7_PAGE_COUNTER    0x00f5
#define    RTL8367D_PORT7_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_PORT7_PAGE_COUNTER_MASK    0x7F

#define    RTL8367D_REG_PAGEMETER_PORT7_CTRL0    0x00f6

#define    RTL8367D_REG_PAGEMETER_PORT7_CTRL1    0x00f7

#define    RTL8367D_REG_PORT7_EEECFG    0x00f8
#define    RTL8367D_PORT7_EEECFG_EEE_PORT_TX_EN_OFFSET    9
#define    RTL8367D_PORT7_EEECFG_EEE_PORT_TX_EN_MASK    0x200
#define    RTL8367D_PORT7_EEECFG_EEE_PORT_RX_EN_OFFSET    8
#define    RTL8367D_PORT7_EEECFG_EEE_PORT_RX_EN_MASK    0x100
#define    RTL8367D_PORT7_EEECFG_EEE_LPI_OFFSET    5
#define    RTL8367D_PORT7_EEECFG_EEE_LPI_MASK    0x20
#define    RTL8367D_PORT7_EEECFG_EEE_TX_STS_OFFSET    4
#define    RTL8367D_PORT7_EEECFG_EEE_TX_STS_MASK    0x10
#define    RTL8367D_PORT7_EEECFG_EEE_RX_STS_OFFSET    3
#define    RTL8367D_PORT7_EEECFG_EEE_RX_STS_MASK    0x8
#define    RTL8367D_PORT7_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2
#define    RTL8367D_PORT7_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4

#define    RTL8367D_REG_PORT7_EEETXMTR    0x00f9

#define    RTL8367D_REG_PORT7_EEERXMTR    0x00fa

#define    RTL8367D_REG_PORT7_DUMMY    0x00fe

#define    RTL8367D_REG_P7_MSIC1    0x00ff
#define    RTL8367D_P7_MSIC1_OFFSET    0
#define    RTL8367D_P7_MSIC1_MASK    0x1

/* (16'h0200)outq_reg */

#define    RTL8367D_REG_FLOWCTRL_QUEUE0_DROP_ON    0x0200
#define    RTL8367D_FLOWCTRL_QUEUE0_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE0_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE1_DROP_ON    0x0201
#define    RTL8367D_FLOWCTRL_QUEUE1_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE1_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE2_DROP_ON    0x0202
#define    RTL8367D_FLOWCTRL_QUEUE2_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE2_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE3_DROP_ON    0x0203
#define    RTL8367D_FLOWCTRL_QUEUE3_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE3_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE4_DROP_ON    0x0204
#define    RTL8367D_FLOWCTRL_QUEUE4_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE4_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE5_DROP_ON    0x0205
#define    RTL8367D_FLOWCTRL_QUEUE5_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE5_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE6_DROP_ON    0x0206
#define    RTL8367D_FLOWCTRL_QUEUE6_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE6_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE7_DROP_ON    0x0207
#define    RTL8367D_FLOWCTRL_QUEUE7_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE7_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT0_DROP_ON    0x0208
#define    RTL8367D_FLOWCTRL_PORT0_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT0_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT1_DROP_ON    0x0209
#define    RTL8367D_FLOWCTRL_PORT1_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT1_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT2_DROP_ON    0x020a
#define    RTL8367D_FLOWCTRL_PORT2_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT2_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT3_DROP_ON    0x020b
#define    RTL8367D_FLOWCTRL_PORT3_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT3_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT4_DROP_ON    0x020c
#define    RTL8367D_FLOWCTRL_PORT4_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT4_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT5_DROP_ON    0x020d
#define    RTL8367D_FLOWCTRL_PORT5_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT5_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT6_DROP_ON    0x020e
#define    RTL8367D_FLOWCTRL_PORT6_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT6_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT7_DROP_ON    0x020f
#define    RTL8367D_FLOWCTRL_PORT7_DROP_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT7_DROP_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT_GAP    0x0218
#define    RTL8367D_FLOWCTRL_PORT_GAP_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT_GAP_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE_GAP    0x0219
#define    RTL8367D_FLOWCTRL_QUEUE_GAP_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE_GAP_MASK    0x7FF

#define    RTL8367D_REG_PORT_QEMPTY    0x022d
#define    RTL8367D_PORT_QEMPTY_OFFSET    0
#define    RTL8367D_PORT_QEMPTY_MASK    0xFF

#define    RTL8367D_REG_FLOWCTRL_DEBUG_CTRL0    0x022e
#define    RTL8367D_FLOWCTRL_DEBUG_CTRL0_OFFSET    0
#define    RTL8367D_FLOWCTRL_DEBUG_CTRL0_MASK    0x7

#define    RTL8367D_REG_FLOWCTRL_DEBUG_CTRL1    0x022f
#define    RTL8367D_TOTAL_OFFSET    9
#define    RTL8367D_TOTAL_MASK    0x200
#define    RTL8367D_PORT_MAX_OFFSET    8
#define    RTL8367D_PORT_MAX_MASK    0x100
#define    RTL8367D_QMAX_MASK_OFFSET    0
#define    RTL8367D_QMAX_MASK_MASK    0xFF

#define    RTL8367D_REG_FLOWCTRL_QUEUE0_PAGE_COUNT    0x0230
#define    RTL8367D_FLOWCTRL_QUEUE0_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE0_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE1_PAGE_COUNT    0x0231
#define    RTL8367D_FLOWCTRL_QUEUE1_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE1_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE2_PAGE_COUNT    0x0232
#define    RTL8367D_FLOWCTRL_QUEUE2_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE2_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE3_PAGE_COUNT    0x0233
#define    RTL8367D_FLOWCTRL_QUEUE3_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE3_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE4_PAGE_COUNT    0x0234
#define    RTL8367D_FLOWCTRL_QUEUE4_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE4_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE5_PAGE_COUNT    0x0235
#define    RTL8367D_FLOWCTRL_QUEUE5_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE5_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE6_PAGE_COUNT    0x0236
#define    RTL8367D_FLOWCTRL_QUEUE6_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE6_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE7_PAGE_COUNT    0x0237
#define    RTL8367D_FLOWCTRL_QUEUE7_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE7_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT_PAGE_COUNT    0x0238
#define    RTL8367D_FLOWCTRL_PORT_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT    0x0239
#define    RTL8367D_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT    0x023a
#define    RTL8367D_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT    0x023b
#define    RTL8367D_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT    0x023c
#define    RTL8367D_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT    0x023d
#define    RTL8367D_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT    0x023e
#define    RTL8367D_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT    0x023f
#define    RTL8367D_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT    0x0240
#define    RTL8367D_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT_MAX_PAGE_COUNT    0x0241
#define    RTL8367D_FLOWCTRL_PORT_MAX_PAGE_COUNT_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT_MAX_PAGE_COUNT_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_TOTAL_PACKET_COUNT    0x0243

#define    RTL8367D_REG_HIGH_QUEUE_MASK0    0x0244
#define    RTL8367D_PORT1_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8367D_PORT1_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8367D_PORT0_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8367D_PORT0_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8367D_REG_HIGH_QUEUE_MASK1    0x0245
#define    RTL8367D_PORT3_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8367D_PORT3_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8367D_PORT2_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8367D_PORT2_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8367D_REG_HIGH_QUEUE_MASK2    0x0246
#define    RTL8367D_PORT5_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8367D_PORT5_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8367D_PORT4_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8367D_PORT4_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8367D_REG_HIGH_QUEUE_MASK3    0x0247
#define    RTL8367D_PORT7_HIGH_QUEUE_MASK_OFFSET    8
#define    RTL8367D_PORT7_HIGH_QUEUE_MASK_MASK    0xFF00
#define    RTL8367D_PORT6_HIGH_QUEUE_MASK_OFFSET    0
#define    RTL8367D_PORT6_HIGH_QUEUE_MASK_MASK    0xFF

#define    RTL8367D_REG_LOW_QUEUE_TH    0x024c
#define    RTL8367D_LOW_QUEUE_TH_OFFSET    0
#define    RTL8367D_LOW_QUEUE_TH_MASK    0x7FF

#define    RTL8367D_REG_TH_TX_PREFET    0x0250
#define    RTL8367D_TH_TX_PREFET_OFFSET    0
#define    RTL8367D_TH_TX_PREFET_MASK    0xFF

/* (16'h0300)sch_reg */

#define    RTL8367D_REG_SCHEDULE_WFQ_CTRL    0x0300
#define    RTL8367D_SCHEDULE_WFQ_CTRL_OFFSET    0
#define    RTL8367D_SCHEDULE_WFQ_CTRL_MASK    0x1

#define    RTL8367D_REG_SCHEDULE_WFQ_BURST_SIZE    0x0301

#define    RTL8367D_REG_SCHEDULE_QUEUE_TYPE_CTRL0    0x0302
#define    RTL8367D_PORT1_QUEUE7_TYPE_OFFSET    15
#define    RTL8367D_PORT1_QUEUE7_TYPE_MASK    0x8000
#define    RTL8367D_PORT1_QUEUE6_TYPE_OFFSET    14
#define    RTL8367D_PORT1_QUEUE6_TYPE_MASK    0x4000
#define    RTL8367D_PORT1_QUEUE5_TYPE_OFFSET    13
#define    RTL8367D_PORT1_QUEUE5_TYPE_MASK    0x2000
#define    RTL8367D_PORT1_QUEUE4_TYPE_OFFSET    12
#define    RTL8367D_PORT1_QUEUE4_TYPE_MASK    0x1000
#define    RTL8367D_PORT1_QUEUE3_TYPE_OFFSET    11
#define    RTL8367D_PORT1_QUEUE3_TYPE_MASK    0x800
#define    RTL8367D_PORT1_QUEUE2_TYPE_OFFSET    10
#define    RTL8367D_PORT1_QUEUE2_TYPE_MASK    0x400
#define    RTL8367D_PORT1_QUEUE1_TYPE_OFFSET    9
#define    RTL8367D_PORT1_QUEUE1_TYPE_MASK    0x200
#define    RTL8367D_PORT1_QUEUE0_TYPE_OFFSET    8
#define    RTL8367D_PORT1_QUEUE0_TYPE_MASK    0x100
#define    RTL8367D_PORT0_QUEUE7_TYPE_OFFSET    7
#define    RTL8367D_PORT0_QUEUE7_TYPE_MASK    0x80
#define    RTL8367D_PORT0_QUEUE6_TYPE_OFFSET    6
#define    RTL8367D_PORT0_QUEUE6_TYPE_MASK    0x40
#define    RTL8367D_PORT0_QUEUE5_TYPE_OFFSET    5
#define    RTL8367D_PORT0_QUEUE5_TYPE_MASK    0x20
#define    RTL8367D_PORT0_QUEUE4_TYPE_OFFSET    4
#define    RTL8367D_PORT0_QUEUE4_TYPE_MASK    0x10
#define    RTL8367D_PORT0_QUEUE3_TYPE_OFFSET    3
#define    RTL8367D_PORT0_QUEUE3_TYPE_MASK    0x8
#define    RTL8367D_PORT0_QUEUE2_TYPE_OFFSET    2
#define    RTL8367D_PORT0_QUEUE2_TYPE_MASK    0x4
#define    RTL8367D_PORT0_QUEUE1_TYPE_OFFSET    1
#define    RTL8367D_PORT0_QUEUE1_TYPE_MASK    0x2
#define    RTL8367D_PORT0_QUEUE0_TYPE_OFFSET    0
#define    RTL8367D_PORT0_QUEUE0_TYPE_MASK    0x1

#define    RTL8367D_REG_SCHEDULE_QUEUE_TYPE_CTRL1    0x0303
#define    RTL8367D_PORT3_QUEUE7_TYPE_OFFSET    15
#define    RTL8367D_PORT3_QUEUE7_TYPE_MASK    0x8000
#define    RTL8367D_PORT3_QUEUE6_TYPE_OFFSET    14
#define    RTL8367D_PORT3_QUEUE6_TYPE_MASK    0x4000
#define    RTL8367D_PORT3_QUEUE5_TYPE_OFFSET    13
#define    RTL8367D_PORT3_QUEUE5_TYPE_MASK    0x2000
#define    RTL8367D_PORT3_QUEUE4_TYPE_OFFSET    12
#define    RTL8367D_PORT3_QUEUE4_TYPE_MASK    0x1000
#define    RTL8367D_PORT3_QUEUE3_TYPE_OFFSET    11
#define    RTL8367D_PORT3_QUEUE3_TYPE_MASK    0x800
#define    RTL8367D_PORT3_QUEUE2_TYPE_OFFSET    10
#define    RTL8367D_PORT3_QUEUE2_TYPE_MASK    0x400
#define    RTL8367D_PORT3_QUEUE1_TYPE_OFFSET    9
#define    RTL8367D_PORT3_QUEUE1_TYPE_MASK    0x200
#define    RTL8367D_PORT3_QUEUE0_TYPE_OFFSET    8
#define    RTL8367D_PORT3_QUEUE0_TYPE_MASK    0x100
#define    RTL8367D_PORT2_QUEUE7_TYPE_OFFSET    7
#define    RTL8367D_PORT2_QUEUE7_TYPE_MASK    0x80
#define    RTL8367D_PORT2_QUEUE6_TYPE_OFFSET    6
#define    RTL8367D_PORT2_QUEUE6_TYPE_MASK    0x40
#define    RTL8367D_PORT2_QUEUE5_TYPE_OFFSET    5
#define    RTL8367D_PORT2_QUEUE5_TYPE_MASK    0x20
#define    RTL8367D_PORT2_QUEUE4_TYPE_OFFSET    4
#define    RTL8367D_PORT2_QUEUE4_TYPE_MASK    0x10
#define    RTL8367D_PORT2_QUEUE3_TYPE_OFFSET    3
#define    RTL8367D_PORT2_QUEUE3_TYPE_MASK    0x8
#define    RTL8367D_PORT2_QUEUE2_TYPE_OFFSET    2
#define    RTL8367D_PORT2_QUEUE2_TYPE_MASK    0x4
#define    RTL8367D_PORT2_QUEUE1_TYPE_OFFSET    1
#define    RTL8367D_PORT2_QUEUE1_TYPE_MASK    0x2
#define    RTL8367D_PORT2_QUEUE0_TYPE_OFFSET    0
#define    RTL8367D_PORT2_QUEUE0_TYPE_MASK    0x1

#define    RTL8367D_REG_SCHEDULE_QUEUE_TYPE_CTRL2    0x0304
#define    RTL8367D_PORT5_QUEUE7_TYPE_OFFSET    15
#define    RTL8367D_PORT5_QUEUE7_TYPE_MASK    0x8000
#define    RTL8367D_PORT5_QUEUE6_TYPE_OFFSET    14
#define    RTL8367D_PORT5_QUEUE6_TYPE_MASK    0x4000
#define    RTL8367D_PORT5_QUEUE5_TYPE_OFFSET    13
#define    RTL8367D_PORT5_QUEUE5_TYPE_MASK    0x2000
#define    RTL8367D_PORT5_QUEUE4_TYPE_OFFSET    12
#define    RTL8367D_PORT5_QUEUE4_TYPE_MASK    0x1000
#define    RTL8367D_PORT5_QUEUE3_TYPE_OFFSET    11
#define    RTL8367D_PORT5_QUEUE3_TYPE_MASK    0x800
#define    RTL8367D_PORT5_QUEUE2_TYPE_OFFSET    10
#define    RTL8367D_PORT5_QUEUE2_TYPE_MASK    0x400
#define    RTL8367D_PORT5_QUEUE1_TYPE_OFFSET    9
#define    RTL8367D_PORT5_QUEUE1_TYPE_MASK    0x200
#define    RTL8367D_PORT5_QUEUE0_TYPE_OFFSET    8
#define    RTL8367D_PORT5_QUEUE0_TYPE_MASK    0x100
#define    RTL8367D_PORT4_QUEUE7_TYPE_OFFSET    7
#define    RTL8367D_PORT4_QUEUE7_TYPE_MASK    0x80
#define    RTL8367D_PORT4_QUEUE6_TYPE_OFFSET    6
#define    RTL8367D_PORT4_QUEUE6_TYPE_MASK    0x40
#define    RTL8367D_PORT4_QUEUE5_TYPE_OFFSET    5
#define    RTL8367D_PORT4_QUEUE5_TYPE_MASK    0x20
#define    RTL8367D_PORT4_QUEUE4_TYPE_OFFSET    4
#define    RTL8367D_PORT4_QUEUE4_TYPE_MASK    0x10
#define    RTL8367D_PORT4_QUEUE3_TYPE_OFFSET    3
#define    RTL8367D_PORT4_QUEUE3_TYPE_MASK    0x8
#define    RTL8367D_PORT4_QUEUE2_TYPE_OFFSET    2
#define    RTL8367D_PORT4_QUEUE2_TYPE_MASK    0x4
#define    RTL8367D_PORT4_QUEUE1_TYPE_OFFSET    1
#define    RTL8367D_PORT4_QUEUE1_TYPE_MASK    0x2
#define    RTL8367D_PORT4_QUEUE0_TYPE_OFFSET    0
#define    RTL8367D_PORT4_QUEUE0_TYPE_MASK    0x1

#define    RTL8367D_REG_SCHEDULE_QUEUE_TYPE_CTRL3    0x0305
#define    RTL8367D_PORT7_QUEUE7_TYPE_OFFSET    15
#define    RTL8367D_PORT7_QUEUE7_TYPE_MASK    0x8000
#define    RTL8367D_PORT7_QUEUE6_TYPE_OFFSET    14
#define    RTL8367D_PORT7_QUEUE6_TYPE_MASK    0x4000
#define    RTL8367D_PORT7_QUEUE5_TYPE_OFFSET    13
#define    RTL8367D_PORT7_QUEUE5_TYPE_MASK    0x2000
#define    RTL8367D_PORT7_QUEUE4_TYPE_OFFSET    12
#define    RTL8367D_PORT7_QUEUE4_TYPE_MASK    0x1000
#define    RTL8367D_PORT7_QUEUE3_TYPE_OFFSET    11
#define    RTL8367D_PORT7_QUEUE3_TYPE_MASK    0x800
#define    RTL8367D_PORT7_QUEUE2_TYPE_OFFSET    10
#define    RTL8367D_PORT7_QUEUE2_TYPE_MASK    0x400
#define    RTL8367D_PORT7_QUEUE1_TYPE_OFFSET    9
#define    RTL8367D_PORT7_QUEUE1_TYPE_MASK    0x200
#define    RTL8367D_PORT7_QUEUE0_TYPE_OFFSET    8
#define    RTL8367D_PORT7_QUEUE0_TYPE_MASK    0x100
#define    RTL8367D_PORT6_QUEUE7_TYPE_OFFSET    7
#define    RTL8367D_PORT6_QUEUE7_TYPE_MASK    0x80
#define    RTL8367D_PORT6_QUEUE6_TYPE_OFFSET    6
#define    RTL8367D_PORT6_QUEUE6_TYPE_MASK    0x40
#define    RTL8367D_PORT6_QUEUE5_TYPE_OFFSET    5
#define    RTL8367D_PORT6_QUEUE5_TYPE_MASK    0x20
#define    RTL8367D_PORT6_QUEUE4_TYPE_OFFSET    4
#define    RTL8367D_PORT6_QUEUE4_TYPE_MASK    0x10
#define    RTL8367D_PORT6_QUEUE3_TYPE_OFFSET    3
#define    RTL8367D_PORT6_QUEUE3_TYPE_MASK    0x8
#define    RTL8367D_PORT6_QUEUE2_TYPE_OFFSET    2
#define    RTL8367D_PORT6_QUEUE2_TYPE_MASK    0x4
#define    RTL8367D_PORT6_QUEUE1_TYPE_OFFSET    1
#define    RTL8367D_PORT6_QUEUE1_TYPE_MASK    0x2
#define    RTL8367D_PORT6_QUEUE0_TYPE_OFFSET    0
#define    RTL8367D_PORT6_QUEUE0_TYPE_MASK    0x1

#define    RTL8367D_REG_SCHEDULE_APR_CTRL0    0x030a
#define    RTL8367D_PORT7_APR_ENABLE_OFFSET    7
#define    RTL8367D_PORT7_APR_ENABLE_MASK    0x80
#define    RTL8367D_PORT6_APR_ENABLE_OFFSET    6
#define    RTL8367D_PORT6_APR_ENABLE_MASK    0x40
#define    RTL8367D_PORT5_APR_ENABLE_OFFSET    5
#define    RTL8367D_PORT5_APR_ENABLE_MASK    0x20
#define    RTL8367D_PORT4_APR_ENABLE_OFFSET    4
#define    RTL8367D_PORT4_APR_ENABLE_MASK    0x10
#define    RTL8367D_PORT3_APR_ENABLE_OFFSET    3
#define    RTL8367D_PORT3_APR_ENABLE_MASK    0x8
#define    RTL8367D_PORT2_APR_ENABLE_OFFSET    2
#define    RTL8367D_PORT2_APR_ENABLE_MASK    0x4
#define    RTL8367D_PORT1_APR_ENABLE_OFFSET    1
#define    RTL8367D_PORT1_APR_ENABLE_MASK    0x2
#define    RTL8367D_PORT0_APR_ENABLE_OFFSET    0
#define    RTL8367D_PORT0_APR_ENABLE_MASK    0x1

#define    RTL8367D_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT    0x030c

#define    RTL8367D_REG_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT    0x030d
#define    RTL8367D_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT    0x030e
#define    RTL8367D_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT    0x030f
#define    RTL8367D_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT    0x0310
#define    RTL8367D_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT    0x0311
#define    RTL8367D_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT    0x0312
#define    RTL8367D_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT    0x0313
#define    RTL8367D_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT1_QUEUE0_WFQ_WEIGHT    0x0314

#define    RTL8367D_REG_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT    0x0315
#define    RTL8367D_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT    0x0316
#define    RTL8367D_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT    0x0317
#define    RTL8367D_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT    0x0318
#define    RTL8367D_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT    0x0319
#define    RTL8367D_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT    0x031a
#define    RTL8367D_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT    0x031b
#define    RTL8367D_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT2_QUEUE0_WFQ_WEIGHT    0x031c

#define    RTL8367D_REG_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT    0x031d
#define    RTL8367D_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT    0x031e
#define    RTL8367D_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT    0x031f
#define    RTL8367D_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT    0x0320
#define    RTL8367D_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT    0x0321
#define    RTL8367D_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT    0x0322
#define    RTL8367D_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT    0x0323
#define    RTL8367D_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT3_QUEUE0_WFQ_WEIGHT    0x0324

#define    RTL8367D_REG_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT    0x0325
#define    RTL8367D_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT    0x0326
#define    RTL8367D_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT    0x0327
#define    RTL8367D_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT    0x0328
#define    RTL8367D_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT    0x0329
#define    RTL8367D_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT    0x032a
#define    RTL8367D_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT    0x032b
#define    RTL8367D_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT4_QUEUE0_WFQ_WEIGHT    0x032c

#define    RTL8367D_REG_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT    0x032d
#define    RTL8367D_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT    0x032e
#define    RTL8367D_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT    0x032f
#define    RTL8367D_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT    0x0330
#define    RTL8367D_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT    0x0331
#define    RTL8367D_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT    0x0332
#define    RTL8367D_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT    0x0333
#define    RTL8367D_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT5_QUEUE0_WFQ_WEIGHT    0x0334

#define    RTL8367D_REG_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT    0x0335
#define    RTL8367D_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT    0x0336
#define    RTL8367D_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT    0x0337
#define    RTL8367D_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT    0x0338
#define    RTL8367D_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT    0x0339
#define    RTL8367D_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT    0x033a
#define    RTL8367D_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT    0x033b
#define    RTL8367D_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT6_QUEUE0_WFQ_WEIGHT    0x033c

#define    RTL8367D_REG_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT    0x033d
#define    RTL8367D_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT    0x033e
#define    RTL8367D_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT    0x033f
#define    RTL8367D_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT    0x0340
#define    RTL8367D_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT    0x0341
#define    RTL8367D_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT    0x0342
#define    RTL8367D_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT    0x0343
#define    RTL8367D_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT7_QUEUE0_WFQ_WEIGHT    0x0344

#define    RTL8367D_REG_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT    0x0345
#define    RTL8367D_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT    0x0346
#define    RTL8367D_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT    0x0347
#define    RTL8367D_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT    0x0348
#define    RTL8367D_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT    0x0349
#define    RTL8367D_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT    0x034a
#define    RTL8367D_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT    0x034b
#define    RTL8367D_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_MASK    0x7F

#define    RTL8367D_REG_PORT0_EGRESSBW_CTRL0    0x038c

#define    RTL8367D_REG_PORT0_EGRESSBW_CTRL1    0x038d
#define    RTL8367D_PORT0_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8367D_PORT0_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8367D_REG_PORT1_EGRESSBW_CTRL0    0x038e

#define    RTL8367D_REG_PORT1_EGRESSBW_CTRL1    0x038f
#define    RTL8367D_PORT1_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8367D_PORT1_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8367D_REG_PORT2_EGRESSBW_CTRL0    0x0390

#define    RTL8367D_REG_PORT2_EGRESSBW_CTRL1    0x0391
#define    RTL8367D_PORT2_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8367D_PORT2_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8367D_REG_PORT3_EGRESSBW_CTRL0    0x0392

#define    RTL8367D_REG_PORT3_EGRESSBW_CTRL1    0x0393
#define    RTL8367D_PORT3_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8367D_PORT3_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8367D_REG_PORT4_EGRESSBW_CTRL0    0x0394

#define    RTL8367D_REG_PORT4_EGRESSBW_CTRL1    0x0395
#define    RTL8367D_PORT4_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8367D_PORT4_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8367D_REG_PORT5_EGRESSBW_CTRL0    0x0396

#define    RTL8367D_REG_PORT5_EGRESSBW_CTRL1    0x0397
#define    RTL8367D_PORT5_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8367D_PORT5_EGRESSBW_CTRL1_MASK    0x1

#define    RTL8367D_REG_PORT6_EGRESSBW_CTRL0    0x0398

#define    RTL8367D_REG_PORT6_EGRESSBW_CTRL1    0x0399
#define    RTL8367D_PORT6_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8367D_PORT6_EGRESSBW_CTRL1_MASK    0x7

#define    RTL8367D_REG_PORT7_EGRESSBW_CTRL0    0x039a

#define    RTL8367D_REG_PORT7_EGRESSBW_CTRL1    0x039b
#define    RTL8367D_PORT7_EGRESSBW_CTRL1_OFFSET    0
#define    RTL8367D_PORT7_EGRESSBW_CTRL1_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT0_APR_METER_CTRL0    0x03ac
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT0_APR_METER_CTRL1    0x03ad
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT1_APR_METER_CTRL0    0x03b0
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT1_APR_METER_CTRL1    0x03b1
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT2_APR_METER_CTRL0    0x03b4
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT2_APR_METER_CTRL1    0x03b5
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT3_APR_METER_CTRL0    0x03b8
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT3_APR_METER_CTRL1    0x03b9
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT4_APR_METER_CTRL0    0x03bc
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT4_APR_METER_CTRL1    0x03bd
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT5_APR_METER_CTRL0    0x03c0
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT5_APR_METER_CTRL1    0x03c1
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT6_APR_METER_CTRL0    0x03c4
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT6_APR_METER_CTRL1    0x03c5
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT7_APR_METER_CTRL0    0x03c8
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7

#define    RTL8367D_REG_SCHEDULE_PORT7_APR_METER_CTRL1    0x03c9
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0
#define    RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7

#define    RTL8367D_REG_LINE_RATE_1G_L    0x03ec

#define    RTL8367D_REG_LINE_RATE_1G_H    0x03ed
#define    RTL8367D_LINE_RATE_1G_H_OFFSET    0
#define    RTL8367D_LINE_RATE_1G_H_MASK    0x1

#define    RTL8367D_REG_LINE_RATE_100_L    0x03ee

#define    RTL8367D_REG_LINE_RATE_100_H    0x03ef
#define    RTL8367D_LINE_RATE_100_H_OFFSET    0
#define    RTL8367D_LINE_RATE_100_H_MASK    0x1

#define    RTL8367D_REG_LINE_RATE_10_L    0x03f0

#define    RTL8367D_REG_LINE_RATE_10_H    0x03f1
#define    RTL8367D_LINE_RATE_10_H_OFFSET    0
#define    RTL8367D_LINE_RATE_10_H_MASK    0x1

#define    RTL8367D_REG_BYPASS_LINE_RATE    0x03f7
#define    RTL8367D_BYPASS_PORT7_CONSTRAINT_OFFSET    2
#define    RTL8367D_BYPASS_PORT7_CONSTRAINT_MASK    0x4
#define    RTL8367D_BYPASS_PORT6_CONSTRAINT_OFFSET    1
#define    RTL8367D_BYPASS_PORT6_CONSTRAINT_MASK    0x2
#define    RTL8367D_BYPASS_PORT5_CONSTRAINT_OFFSET    0
#define    RTL8367D_BYPASS_PORT5_CONSTRAINT_MASK    0x1

#define    RTL8367D_REG_LINE_RATE_500_H    0x03f8
#define    RTL8367D_LINE_RATE_500_H_OFFSET    0
#define    RTL8367D_LINE_RATE_500_H_MASK    0x7

#define    RTL8367D_REG_LINE_RATE_500_L    0x03f9

#define    RTL8367D_REG_LINE_RATE_HSG_H    0x03fa
#define    RTL8367D_LINE_RATE_HSG_H_OFFSET    0
#define    RTL8367D_LINE_RATE_HSG_H_MASK    0x7

#define    RTL8367D_REG_LINE_RATE_HSG_L    0x03fb

#define    RTL8367D_REG_SCH_WRR_OPT    0x03fc
#define    RTL8367D_CFG_WRR_MODE_OFFSET    14
#define    RTL8367D_CFG_WRR_MODE_MASK    0x4000
#define    RTL8367D_CFG_WRR_PKTLEN_OFFSET    0
#define    RTL8367D_CFG_WRR_PKTLEN_MASK    0x3FFF

/* (16'h0500)table_reg */

#define    RTL8367D_REG_TABLE_ACCESS_CTRL    0x0500
#define    RTL8367D_TABLE_ACCESS_CTRL_SPA_OFFSET    8
#define    RTL8367D_TABLE_ACCESS_CTRL_SPA_MASK    0x700
#define    RTL8367D_ACCESS_METHOD_OFFSET    4
#define    RTL8367D_ACCESS_METHOD_MASK    0x70
#define    RTL8367D_COMMAND_TYPE_OFFSET    3
#define    RTL8367D_COMMAND_TYPE_MASK    0x8
#define    RTL8367D_TABLE_TYPE_OFFSET    0
#define    RTL8367D_TABLE_TYPE_MASK    0x7

#define    RTL8367D_REG_TABLE_ACCESS_ADDR    0x0501
#define    RTL8367D_TABLE_ACCESS_ADDR_OFFSET    0
#define    RTL8367D_TABLE_ACCESS_ADDR_MASK    0xFFF

#define    RTL8367D_REG_TABLE_LUT_ADDR    0x0502
#define    RTL8367D_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET    13
#define    RTL8367D_TABLE_LUT_ADDR_BUSY_FLAG_MASK    0x2000
#define    RTL8367D_HIT_STATUS_OFFSET    12
#define    RTL8367D_HIT_STATUS_MASK    0x1000
#define    RTL8367D_TYPE_OFFSET    11
#define    RTL8367D_TYPE_MASK    0x800
#define    RTL8367D_TABLE_LUT_ADDR_ADDRESS_OFFSET    0
#define    RTL8367D_TABLE_LUT_ADDR_ADDRESS_MASK    0x7FF

#define    RTL8367D_REG_HSA_HSB_LATCH    0x0503
#define    RTL8367D_LATCH_ALWAYS_OFFSET    15
#define    RTL8367D_LATCH_ALWAYS_MASK    0x8000
#define    RTL8367D_LATCH_FIRST_OFFSET    14
#define    RTL8367D_LATCH_FIRST_MASK    0x4000
#define    RTL8367D_SPA_EN_OFFSET    13
#define    RTL8367D_SPA_EN_MASK    0x2000
#define    RTL8367D_FORWARD_EN_OFFSET    12
#define    RTL8367D_FORWARD_EN_MASK    0x1000
#define    RTL8367D_REASON_EN_OFFSET    11
#define    RTL8367D_REASON_EN_MASK    0x800
#define    RTL8367D_HSA_HSB_LATCH_SPA_OFFSET    8
#define    RTL8367D_HSA_HSB_LATCH_SPA_MASK    0x700
#define    RTL8367D_FORWARD_OFFSET    6
#define    RTL8367D_FORWARD_MASK    0xC0
#define    RTL8367D_REASON_OFFSET    0
#define    RTL8367D_REASON_MASK    0x3F

#define    RTL8367D_REG_TABLE_WRITE_DATA0    0x0510

#define    RTL8367D_REG_TABLE_WRITE_DATA1    0x0511

#define    RTL8367D_REG_TABLE_WRITE_DATA2    0x0512

#define    RTL8367D_REG_TABLE_WRITE_DATA3    0x0513

#define    RTL8367D_REG_TABLE_WRITE_DATA4    0x0514

#define    RTL8367D_REG_TABLE_WRITE_DATA5    0x0515

#define    RTL8367D_REG_TABLE_WRITE_DATA6    0x0516

#define    RTL8367D_REG_TABLE_WRITE_DATA7    0x0517

#define    RTL8367D_REG_TABLE_WRITE_DATA8    0x0518

#define    RTL8367D_REG_TABLE_WRITE_DATA9    0x0519
#define    RTL8367D_TABLE_WRITE_DATA9_OFFSET    0
#define    RTL8367D_TABLE_WRITE_DATA9_MASK    0x1

#define    RTL8367D_REG_TABLE_READ_DATA0    0x0520

#define    RTL8367D_REG_TABLE_READ_DATA1    0x0521

#define    RTL8367D_REG_TABLE_READ_DATA2    0x0522

#define    RTL8367D_REG_TABLE_READ_DATA3    0x0523

#define    RTL8367D_REG_TABLE_READ_DATA4    0x0524

#define    RTL8367D_REG_TABLE_READ_DATA5    0x0525

#define    RTL8367D_REG_TABLE_READ_DATA6    0x0526

#define    RTL8367D_REG_TABLE_READ_DATA7    0x0527

#define    RTL8367D_REG_TABLE_READ_DATA8    0x0528

#define    RTL8367D_REG_TABLE_READ_DATA9    0x0529
#define    RTL8367D_TABLE_READ_DATA9_OFFSET    0
#define    RTL8367D_TABLE_READ_DATA9_MASK    0x1

/* (16'h0600)acl_reg */

#define    RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL0    0x0600
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL0_FIELD1_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL0_FIELD1_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL0_FIELD0_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL0_FIELD0_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL1    0x0601
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL1_FIELD3_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL1_FIELD3_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL1_FIELD2_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL1_FIELD2_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL2    0x0602
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL2_FIELD5_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL2_FIELD5_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL2_FIELD4_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL2_FIELD4_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL3    0x0603
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL3_FIELD7_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL3_FIELD7_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL3_FIELD6_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE0_CTRL3_FIELD6_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE1_CTRL0    0x0604
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL0_FIELD1_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL0_FIELD1_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL0_FIELD0_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL0_FIELD0_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE1_CTRL1    0x0605
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL1_FIELD3_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL1_FIELD3_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL1_FIELD2_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL1_FIELD2_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE1_CTRL2    0x0606
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL2_FIELD5_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL2_FIELD5_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL2_FIELD4_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL2_FIELD4_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE1_CTRL3    0x0607
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL3_FIELD7_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL3_FIELD7_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL3_FIELD6_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE1_CTRL3_FIELD6_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE2_CTRL0    0x0608
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL0_FIELD1_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL0_FIELD1_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL0_FIELD0_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL0_FIELD0_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE2_CTRL1    0x0609
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL1_FIELD3_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL1_FIELD3_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL1_FIELD2_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL1_FIELD2_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE2_CTRL2    0x060a
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL2_FIELD5_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL2_FIELD5_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL2_FIELD4_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL2_FIELD4_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE2_CTRL3    0x060b
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL3_FIELD7_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL3_FIELD7_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL3_FIELD6_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE2_CTRL3_FIELD6_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE3_CTRL0    0x060c
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL0_FIELD1_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL0_FIELD1_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL0_FIELD0_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL0_FIELD0_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE3_CTRL1    0x060d
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL1_FIELD3_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL1_FIELD3_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL1_FIELD2_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL1_FIELD2_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE3_CTRL2    0x060e
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL2_FIELD5_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL2_FIELD5_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL2_FIELD4_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL2_FIELD4_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE3_CTRL3    0x060f
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL3_FIELD7_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL3_FIELD7_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL3_FIELD6_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE3_CTRL3_FIELD6_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE4_CTRL0    0x0610
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL0_FIELD1_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL0_FIELD1_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL0_FIELD0_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL0_FIELD0_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE4_CTRL1    0x0611
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL1_FIELD3_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL1_FIELD3_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL1_FIELD2_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL1_FIELD2_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE4_CTRL2    0x0612
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL2_FIELD5_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL2_FIELD5_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL2_FIELD4_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL2_FIELD4_MASK    0x7F

#define    RTL8367D_REG_ACL_RULE_TEMPLATE4_CTRL3    0x0613
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL3_FIELD7_OFFSET    8
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL3_FIELD7_MASK    0x7F00
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL3_FIELD6_OFFSET    0
#define    RTL8367D_ACL_RULE_TEMPLATE4_CTRL3_FIELD6_MASK    0x7F

#define    RTL8367D_REG_ACL_ACTION_CTRL0    0x0614
#define    RTL8367D_OP1_NOT_OFFSET    14
#define    RTL8367D_OP1_NOT_MASK    0x4000
#define    RTL8367D_ACT1_GPIO_OFFSET    13
#define    RTL8367D_ACT1_GPIO_MASK    0x2000
#define    RTL8367D_ACT1_FORWARD_OFFSET    12
#define    RTL8367D_ACT1_FORWARD_MASK    0x1000
#define    RTL8367D_ACT1_POLICING_OFFSET    11
#define    RTL8367D_ACT1_POLICING_MASK    0x800
#define    RTL8367D_ACT1_PRIORITY_OFFSET    10
#define    RTL8367D_ACT1_PRIORITY_MASK    0x400
#define    RTL8367D_ACT1_SVID_OFFSET    9
#define    RTL8367D_ACT1_SVID_MASK    0x200
#define    RTL8367D_ACT1_CVID_OFFSET    8
#define    RTL8367D_ACT1_CVID_MASK    0x100
#define    RTL8367D_OP0_NOT_OFFSET    6
#define    RTL8367D_OP0_NOT_MASK    0x40
#define    RTL8367D_ACT0_GPIO_OFFSET    5
#define    RTL8367D_ACT0_GPIO_MASK    0x20
#define    RTL8367D_ACT0_FORWARD_OFFSET    4
#define    RTL8367D_ACT0_FORWARD_MASK    0x10
#define    RTL8367D_ACT0_POLICING_OFFSET    3
#define    RTL8367D_ACT0_POLICING_MASK    0x8
#define    RTL8367D_ACT0_PRIORITY_OFFSET    2
#define    RTL8367D_ACT0_PRIORITY_MASK    0x4
#define    RTL8367D_ACT0_SVID_OFFSET    1
#define    RTL8367D_ACT0_SVID_MASK    0x2
#define    RTL8367D_ACT0_CVID_OFFSET    0
#define    RTL8367D_ACT0_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL1    0x0615
#define    RTL8367D_OP3_NOT_OFFSET    14
#define    RTL8367D_OP3_NOT_MASK    0x4000
#define    RTL8367D_ACT3_GPIO_OFFSET    13
#define    RTL8367D_ACT3_GPIO_MASK    0x2000
#define    RTL8367D_ACT3_FORWARD_OFFSET    12
#define    RTL8367D_ACT3_FORWARD_MASK    0x1000
#define    RTL8367D_ACT3_POLICING_OFFSET    11
#define    RTL8367D_ACT3_POLICING_MASK    0x800
#define    RTL8367D_ACT3_PRIORITY_OFFSET    10
#define    RTL8367D_ACT3_PRIORITY_MASK    0x400
#define    RTL8367D_ACT3_SVID_OFFSET    9
#define    RTL8367D_ACT3_SVID_MASK    0x200
#define    RTL8367D_ACT3_CVID_OFFSET    8
#define    RTL8367D_ACT3_CVID_MASK    0x100
#define    RTL8367D_OP2_NOT_OFFSET    6
#define    RTL8367D_OP2_NOT_MASK    0x40
#define    RTL8367D_ACT2_GPIO_OFFSET    5
#define    RTL8367D_ACT2_GPIO_MASK    0x20
#define    RTL8367D_ACT2_FORWARD_OFFSET    4
#define    RTL8367D_ACT2_FORWARD_MASK    0x10
#define    RTL8367D_ACT2_POLICING_OFFSET    3
#define    RTL8367D_ACT2_POLICING_MASK    0x8
#define    RTL8367D_ACT2_PRIORITY_OFFSET    2
#define    RTL8367D_ACT2_PRIORITY_MASK    0x4
#define    RTL8367D_ACT2_SVID_OFFSET    1
#define    RTL8367D_ACT2_SVID_MASK    0x2
#define    RTL8367D_ACT2_CVID_OFFSET    0
#define    RTL8367D_ACT2_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL2    0x0616
#define    RTL8367D_OP5_NOT_OFFSET    14
#define    RTL8367D_OP5_NOT_MASK    0x4000
#define    RTL8367D_ACT5_GPIO_OFFSET    13
#define    RTL8367D_ACT5_GPIO_MASK    0x2000
#define    RTL8367D_ACT5_FORWARD_OFFSET    12
#define    RTL8367D_ACT5_FORWARD_MASK    0x1000
#define    RTL8367D_ACT5_POLICING_OFFSET    11
#define    RTL8367D_ACT5_POLICING_MASK    0x800
#define    RTL8367D_ACT5_PRIORITY_OFFSET    10
#define    RTL8367D_ACT5_PRIORITY_MASK    0x400
#define    RTL8367D_ACT5_SVID_OFFSET    9
#define    RTL8367D_ACT5_SVID_MASK    0x200
#define    RTL8367D_ACT5_CVID_OFFSET    8
#define    RTL8367D_ACT5_CVID_MASK    0x100
#define    RTL8367D_OP4_NOT_OFFSET    6
#define    RTL8367D_OP4_NOT_MASK    0x40
#define    RTL8367D_ACT4_GPIO_OFFSET    5
#define    RTL8367D_ACT4_GPIO_MASK    0x20
#define    RTL8367D_ACT4_FORWARD_OFFSET    4
#define    RTL8367D_ACT4_FORWARD_MASK    0x10
#define    RTL8367D_ACT4_POLICING_OFFSET    3
#define    RTL8367D_ACT4_POLICING_MASK    0x8
#define    RTL8367D_ACT4_PRIORITY_OFFSET    2
#define    RTL8367D_ACT4_PRIORITY_MASK    0x4
#define    RTL8367D_ACT4_SVID_OFFSET    1
#define    RTL8367D_ACT4_SVID_MASK    0x2
#define    RTL8367D_ACT4_CVID_OFFSET    0
#define    RTL8367D_ACT4_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL3    0x0617
#define    RTL8367D_OP7_NOT_OFFSET    14
#define    RTL8367D_OP7_NOT_MASK    0x4000
#define    RTL8367D_ACT7_GPIO_OFFSET    13
#define    RTL8367D_ACT7_GPIO_MASK    0x2000
#define    RTL8367D_ACT7_FORWARD_OFFSET    12
#define    RTL8367D_ACT7_FORWARD_MASK    0x1000
#define    RTL8367D_ACT7_POLICING_OFFSET    11
#define    RTL8367D_ACT7_POLICING_MASK    0x800
#define    RTL8367D_ACT7_PRIORITY_OFFSET    10
#define    RTL8367D_ACT7_PRIORITY_MASK    0x400
#define    RTL8367D_ACT7_SVID_OFFSET    9
#define    RTL8367D_ACT7_SVID_MASK    0x200
#define    RTL8367D_ACT7_CVID_OFFSET    8
#define    RTL8367D_ACT7_CVID_MASK    0x100
#define    RTL8367D_OP6_NOT_OFFSET    6
#define    RTL8367D_OP6_NOT_MASK    0x40
#define    RTL8367D_ACT6_GPIO_OFFSET    5
#define    RTL8367D_ACT6_GPIO_MASK    0x20
#define    RTL8367D_ACT6_FORWARD_OFFSET    4
#define    RTL8367D_ACT6_FORWARD_MASK    0x10
#define    RTL8367D_ACT6_POLICING_OFFSET    3
#define    RTL8367D_ACT6_POLICING_MASK    0x8
#define    RTL8367D_ACT6_PRIORITY_OFFSET    2
#define    RTL8367D_ACT6_PRIORITY_MASK    0x4
#define    RTL8367D_ACT6_SVID_OFFSET    1
#define    RTL8367D_ACT6_SVID_MASK    0x2
#define    RTL8367D_ACT6_CVID_OFFSET    0
#define    RTL8367D_ACT6_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL4    0x0618
#define    RTL8367D_OP9_NOT_OFFSET    14
#define    RTL8367D_OP9_NOT_MASK    0x4000
#define    RTL8367D_ACT9_GPIO_OFFSET    13
#define    RTL8367D_ACT9_GPIO_MASK    0x2000
#define    RTL8367D_ACT9_FORWARD_OFFSET    12
#define    RTL8367D_ACT9_FORWARD_MASK    0x1000
#define    RTL8367D_ACT9_POLICING_OFFSET    11
#define    RTL8367D_ACT9_POLICING_MASK    0x800
#define    RTL8367D_ACT9_PRIORITY_OFFSET    10
#define    RTL8367D_ACT9_PRIORITY_MASK    0x400
#define    RTL8367D_ACT9_SVID_OFFSET    9
#define    RTL8367D_ACT9_SVID_MASK    0x200
#define    RTL8367D_ACT9_CVID_OFFSET    8
#define    RTL8367D_ACT9_CVID_MASK    0x100
#define    RTL8367D_OP8_NOT_OFFSET    6
#define    RTL8367D_OP8_NOT_MASK    0x40
#define    RTL8367D_ACT8_GPIO_OFFSET    5
#define    RTL8367D_ACT8_GPIO_MASK    0x20
#define    RTL8367D_ACT8_FORWARD_OFFSET    4
#define    RTL8367D_ACT8_FORWARD_MASK    0x10
#define    RTL8367D_ACT8_POLICING_OFFSET    3
#define    RTL8367D_ACT8_POLICING_MASK    0x8
#define    RTL8367D_ACT8_PRIORITY_OFFSET    2
#define    RTL8367D_ACT8_PRIORITY_MASK    0x4
#define    RTL8367D_ACT8_SVID_OFFSET    1
#define    RTL8367D_ACT8_SVID_MASK    0x2
#define    RTL8367D_ACT8_CVID_OFFSET    0
#define    RTL8367D_ACT8_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL5    0x0619
#define    RTL8367D_OP11_NOT_OFFSET    14
#define    RTL8367D_OP11_NOT_MASK    0x4000
#define    RTL8367D_ACT11_GPIO_OFFSET    13
#define    RTL8367D_ACT11_GPIO_MASK    0x2000
#define    RTL8367D_ACT11_FORWARD_OFFSET    12
#define    RTL8367D_ACT11_FORWARD_MASK    0x1000
#define    RTL8367D_ACT11_POLICING_OFFSET    11
#define    RTL8367D_ACT11_POLICING_MASK    0x800
#define    RTL8367D_ACT11_PRIORITY_OFFSET    10
#define    RTL8367D_ACT11_PRIORITY_MASK    0x400
#define    RTL8367D_ACT11_SVID_OFFSET    9
#define    RTL8367D_ACT11_SVID_MASK    0x200
#define    RTL8367D_ACT11_CVID_OFFSET    8
#define    RTL8367D_ACT11_CVID_MASK    0x100
#define    RTL8367D_OP10_NOT_OFFSET    6
#define    RTL8367D_OP10_NOT_MASK    0x40
#define    RTL8367D_ACT10_GPIO_OFFSET    5
#define    RTL8367D_ACT10_GPIO_MASK    0x20
#define    RTL8367D_ACT10_FORWARD_OFFSET    4
#define    RTL8367D_ACT10_FORWARD_MASK    0x10
#define    RTL8367D_ACT10_POLICING_OFFSET    3
#define    RTL8367D_ACT10_POLICING_MASK    0x8
#define    RTL8367D_ACT10_PRIORITY_OFFSET    2
#define    RTL8367D_ACT10_PRIORITY_MASK    0x4
#define    RTL8367D_ACT10_SVID_OFFSET    1
#define    RTL8367D_ACT10_SVID_MASK    0x2
#define    RTL8367D_ACT10_CVID_OFFSET    0
#define    RTL8367D_ACT10_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL6    0x061a
#define    RTL8367D_OP13_NOT_OFFSET    14
#define    RTL8367D_OP13_NOT_MASK    0x4000
#define    RTL8367D_ACT13_GPIO_OFFSET    13
#define    RTL8367D_ACT13_GPIO_MASK    0x2000
#define    RTL8367D_ACT13_FORWARD_OFFSET    12
#define    RTL8367D_ACT13_FORWARD_MASK    0x1000
#define    RTL8367D_ACT13_POLICING_OFFSET    11
#define    RTL8367D_ACT13_POLICING_MASK    0x800
#define    RTL8367D_ACT13_PRIORITY_OFFSET    10
#define    RTL8367D_ACT13_PRIORITY_MASK    0x400
#define    RTL8367D_ACT13_SVID_OFFSET    9
#define    RTL8367D_ACT13_SVID_MASK    0x200
#define    RTL8367D_ACT13_CVID_OFFSET    8
#define    RTL8367D_ACT13_CVID_MASK    0x100
#define    RTL8367D_OP12_NOT_OFFSET    6
#define    RTL8367D_OP12_NOT_MASK    0x40
#define    RTL8367D_ACT12_GPIO_OFFSET    5
#define    RTL8367D_ACT12_GPIO_MASK    0x20
#define    RTL8367D_ACT12_FORWARD_OFFSET    4
#define    RTL8367D_ACT12_FORWARD_MASK    0x10
#define    RTL8367D_ACT12_POLICING_OFFSET    3
#define    RTL8367D_ACT12_POLICING_MASK    0x8
#define    RTL8367D_ACT12_PRIORITY_OFFSET    2
#define    RTL8367D_ACT12_PRIORITY_MASK    0x4
#define    RTL8367D_ACT12_SVID_OFFSET    1
#define    RTL8367D_ACT12_SVID_MASK    0x2
#define    RTL8367D_ACT12_CVID_OFFSET    0
#define    RTL8367D_ACT12_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL7    0x061b
#define    RTL8367D_OP15_NOT_OFFSET    14
#define    RTL8367D_OP15_NOT_MASK    0x4000
#define    RTL8367D_ACT15_GPIO_OFFSET    13
#define    RTL8367D_ACT15_GPIO_MASK    0x2000
#define    RTL8367D_ACT15_FORWARD_OFFSET    12
#define    RTL8367D_ACT15_FORWARD_MASK    0x1000
#define    RTL8367D_ACT15_POLICING_OFFSET    11
#define    RTL8367D_ACT15_POLICING_MASK    0x800
#define    RTL8367D_ACT15_PRIORITY_OFFSET    10
#define    RTL8367D_ACT15_PRIORITY_MASK    0x400
#define    RTL8367D_ACT15_SVID_OFFSET    9
#define    RTL8367D_ACT15_SVID_MASK    0x200
#define    RTL8367D_ACT15_CVID_OFFSET    8
#define    RTL8367D_ACT15_CVID_MASK    0x100
#define    RTL8367D_OP14_NOT_OFFSET    6
#define    RTL8367D_OP14_NOT_MASK    0x40
#define    RTL8367D_ACT14_GPIO_OFFSET    5
#define    RTL8367D_ACT14_GPIO_MASK    0x20
#define    RTL8367D_ACT14_FORWARD_OFFSET    4
#define    RTL8367D_ACT14_FORWARD_MASK    0x10
#define    RTL8367D_ACT14_POLICING_OFFSET    3
#define    RTL8367D_ACT14_POLICING_MASK    0x8
#define    RTL8367D_ACT14_PRIORITY_OFFSET    2
#define    RTL8367D_ACT14_PRIORITY_MASK    0x4
#define    RTL8367D_ACT14_SVID_OFFSET    1
#define    RTL8367D_ACT14_SVID_MASK    0x2
#define    RTL8367D_ACT14_CVID_OFFSET    0
#define    RTL8367D_ACT14_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL8    0x061c
#define    RTL8367D_OP17_NOT_OFFSET    14
#define    RTL8367D_OP17_NOT_MASK    0x4000
#define    RTL8367D_ACT17_GPIO_OFFSET    13
#define    RTL8367D_ACT17_GPIO_MASK    0x2000
#define    RTL8367D_ACT17_FORWARD_OFFSET    12
#define    RTL8367D_ACT17_FORWARD_MASK    0x1000
#define    RTL8367D_ACT17_POLICING_OFFSET    11
#define    RTL8367D_ACT17_POLICING_MASK    0x800
#define    RTL8367D_ACT17_PRIORITY_OFFSET    10
#define    RTL8367D_ACT17_PRIORITY_MASK    0x400
#define    RTL8367D_ACT17_SVID_OFFSET    9
#define    RTL8367D_ACT17_SVID_MASK    0x200
#define    RTL8367D_ACT17_CVID_OFFSET    8
#define    RTL8367D_ACT17_CVID_MASK    0x100
#define    RTL8367D_OP16_NOT_OFFSET    6
#define    RTL8367D_OP16_NOT_MASK    0x40
#define    RTL8367D_ACT16_GPIO_OFFSET    5
#define    RTL8367D_ACT16_GPIO_MASK    0x20
#define    RTL8367D_ACT16_FORWARD_OFFSET    4
#define    RTL8367D_ACT16_FORWARD_MASK    0x10
#define    RTL8367D_ACT16_POLICING_OFFSET    3
#define    RTL8367D_ACT16_POLICING_MASK    0x8
#define    RTL8367D_ACT16_PRIORITY_OFFSET    2
#define    RTL8367D_ACT16_PRIORITY_MASK    0x4
#define    RTL8367D_ACT16_SVID_OFFSET    1
#define    RTL8367D_ACT16_SVID_MASK    0x2
#define    RTL8367D_ACT16_CVID_OFFSET    0
#define    RTL8367D_ACT16_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL9    0x061d
#define    RTL8367D_OP19_NOT_OFFSET    14
#define    RTL8367D_OP19_NOT_MASK    0x4000
#define    RTL8367D_ACT19_GPIO_OFFSET    13
#define    RTL8367D_ACT19_GPIO_MASK    0x2000
#define    RTL8367D_ACT19_FORWARD_OFFSET    12
#define    RTL8367D_ACT19_FORWARD_MASK    0x1000
#define    RTL8367D_ACT19_POLICING_OFFSET    11
#define    RTL8367D_ACT19_POLICING_MASK    0x800
#define    RTL8367D_ACT19_PRIORITY_OFFSET    10
#define    RTL8367D_ACT19_PRIORITY_MASK    0x400
#define    RTL8367D_ACT19_SVID_OFFSET    9
#define    RTL8367D_ACT19_SVID_MASK    0x200
#define    RTL8367D_ACT19_CVID_OFFSET    8
#define    RTL8367D_ACT19_CVID_MASK    0x100
#define    RTL8367D_OP18_NOT_OFFSET    6
#define    RTL8367D_OP18_NOT_MASK    0x40
#define    RTL8367D_ACT18_GPIO_OFFSET    5
#define    RTL8367D_ACT18_GPIO_MASK    0x20
#define    RTL8367D_ACT18_FORWARD_OFFSET    4
#define    RTL8367D_ACT18_FORWARD_MASK    0x10
#define    RTL8367D_ACT18_POLICING_OFFSET    3
#define    RTL8367D_ACT18_POLICING_MASK    0x8
#define    RTL8367D_ACT18_PRIORITY_OFFSET    2
#define    RTL8367D_ACT18_PRIORITY_MASK    0x4
#define    RTL8367D_ACT18_SVID_OFFSET    1
#define    RTL8367D_ACT18_SVID_MASK    0x2
#define    RTL8367D_ACT18_CVID_OFFSET    0
#define    RTL8367D_ACT18_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL10    0x061e
#define    RTL8367D_OP21_NOT_OFFSET    14
#define    RTL8367D_OP21_NOT_MASK    0x4000
#define    RTL8367D_ACT21_GPIO_OFFSET    13
#define    RTL8367D_ACT21_GPIO_MASK    0x2000
#define    RTL8367D_ACT21_FORWARD_OFFSET    12
#define    RTL8367D_ACT21_FORWARD_MASK    0x1000
#define    RTL8367D_ACT21_POLICING_OFFSET    11
#define    RTL8367D_ACT21_POLICING_MASK    0x800
#define    RTL8367D_ACT21_PRIORITY_OFFSET    10
#define    RTL8367D_ACT21_PRIORITY_MASK    0x400
#define    RTL8367D_ACT21_SVID_OFFSET    9
#define    RTL8367D_ACT21_SVID_MASK    0x200
#define    RTL8367D_ACT21_CVID_OFFSET    8
#define    RTL8367D_ACT21_CVID_MASK    0x100
#define    RTL8367D_OP20_NOT_OFFSET    6
#define    RTL8367D_OP20_NOT_MASK    0x40
#define    RTL8367D_ACT20_GPIO_OFFSET    5
#define    RTL8367D_ACT20_GPIO_MASK    0x20
#define    RTL8367D_ACT20_FORWARD_OFFSET    4
#define    RTL8367D_ACT20_FORWARD_MASK    0x10
#define    RTL8367D_ACT20_POLICING_OFFSET    3
#define    RTL8367D_ACT20_POLICING_MASK    0x8
#define    RTL8367D_ACT20_PRIORITY_OFFSET    2
#define    RTL8367D_ACT20_PRIORITY_MASK    0x4
#define    RTL8367D_ACT20_SVID_OFFSET    1
#define    RTL8367D_ACT20_SVID_MASK    0x2
#define    RTL8367D_ACT20_CVID_OFFSET    0
#define    RTL8367D_ACT20_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL11    0x061f
#define    RTL8367D_OP23_NOT_OFFSET    14
#define    RTL8367D_OP23_NOT_MASK    0x4000
#define    RTL8367D_ACT23_GPIO_OFFSET    13
#define    RTL8367D_ACT23_GPIO_MASK    0x2000
#define    RTL8367D_ACT23_FORWARD_OFFSET    12
#define    RTL8367D_ACT23_FORWARD_MASK    0x1000
#define    RTL8367D_ACT23_POLICING_OFFSET    11
#define    RTL8367D_ACT23_POLICING_MASK    0x800
#define    RTL8367D_ACT23_PRIORITY_OFFSET    10
#define    RTL8367D_ACT23_PRIORITY_MASK    0x400
#define    RTL8367D_ACT23_SVID_OFFSET    9
#define    RTL8367D_ACT23_SVID_MASK    0x200
#define    RTL8367D_ACT23_CVID_OFFSET    8
#define    RTL8367D_ACT23_CVID_MASK    0x100
#define    RTL8367D_OP22_NOT_OFFSET    6
#define    RTL8367D_OP22_NOT_MASK    0x40
#define    RTL8367D_ACT22_GPIO_OFFSET    5
#define    RTL8367D_ACT22_GPIO_MASK    0x20
#define    RTL8367D_ACT22_FORWARD_OFFSET    4
#define    RTL8367D_ACT22_FORWARD_MASK    0x10
#define    RTL8367D_ACT22_POLICING_OFFSET    3
#define    RTL8367D_ACT22_POLICING_MASK    0x8
#define    RTL8367D_ACT22_PRIORITY_OFFSET    2
#define    RTL8367D_ACT22_PRIORITY_MASK    0x4
#define    RTL8367D_ACT22_SVID_OFFSET    1
#define    RTL8367D_ACT22_SVID_MASK    0x2
#define    RTL8367D_ACT22_CVID_OFFSET    0
#define    RTL8367D_ACT22_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL12    0x0620
#define    RTL8367D_OP25_NOT_OFFSET    14
#define    RTL8367D_OP25_NOT_MASK    0x4000
#define    RTL8367D_ACT25_GPIO_OFFSET    13
#define    RTL8367D_ACT25_GPIO_MASK    0x2000
#define    RTL8367D_ACT25_FORWARD_OFFSET    12
#define    RTL8367D_ACT25_FORWARD_MASK    0x1000
#define    RTL8367D_ACT25_POLICING_OFFSET    11
#define    RTL8367D_ACT25_POLICING_MASK    0x800
#define    RTL8367D_ACT25_PRIORITY_OFFSET    10
#define    RTL8367D_ACT25_PRIORITY_MASK    0x400
#define    RTL8367D_ACT25_SVID_OFFSET    9
#define    RTL8367D_ACT25_SVID_MASK    0x200
#define    RTL8367D_ACT25_CVID_OFFSET    8
#define    RTL8367D_ACT25_CVID_MASK    0x100
#define    RTL8367D_OP24_NOT_OFFSET    6
#define    RTL8367D_OP24_NOT_MASK    0x40
#define    RTL8367D_ACT24_GPIO_OFFSET    5
#define    RTL8367D_ACT24_GPIO_MASK    0x20
#define    RTL8367D_ACT24_FORWARD_OFFSET    4
#define    RTL8367D_ACT24_FORWARD_MASK    0x10
#define    RTL8367D_ACT24_POLICING_OFFSET    3
#define    RTL8367D_ACT24_POLICING_MASK    0x8
#define    RTL8367D_ACT24_PRIORITY_OFFSET    2
#define    RTL8367D_ACT24_PRIORITY_MASK    0x4
#define    RTL8367D_ACT24_SVID_OFFSET    1
#define    RTL8367D_ACT24_SVID_MASK    0x2
#define    RTL8367D_ACT24_CVID_OFFSET    0
#define    RTL8367D_ACT24_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL13    0x0621
#define    RTL8367D_OP27_NOT_OFFSET    14
#define    RTL8367D_OP27_NOT_MASK    0x4000
#define    RTL8367D_ACT27_GPIO_OFFSET    13
#define    RTL8367D_ACT27_GPIO_MASK    0x2000
#define    RTL8367D_ACT27_FORWARD_OFFSET    12
#define    RTL8367D_ACT27_FORWARD_MASK    0x1000
#define    RTL8367D_ACT27_POLICING_OFFSET    11
#define    RTL8367D_ACT27_POLICING_MASK    0x800
#define    RTL8367D_ACT27_PRIORITY_OFFSET    10
#define    RTL8367D_ACT27_PRIORITY_MASK    0x400
#define    RTL8367D_ACT27_SVID_OFFSET    9
#define    RTL8367D_ACT27_SVID_MASK    0x200
#define    RTL8367D_ACT27_CVID_OFFSET    8
#define    RTL8367D_ACT27_CVID_MASK    0x100
#define    RTL8367D_OP26_NOT_OFFSET    6
#define    RTL8367D_OP26_NOT_MASK    0x40
#define    RTL8367D_ACT26_GPIO_OFFSET    5
#define    RTL8367D_ACT26_GPIO_MASK    0x20
#define    RTL8367D_ACT26_FORWARD_OFFSET    4
#define    RTL8367D_ACT26_FORWARD_MASK    0x10
#define    RTL8367D_ACT26_POLICING_OFFSET    3
#define    RTL8367D_ACT26_POLICING_MASK    0x8
#define    RTL8367D_ACT26_PRIORITY_OFFSET    2
#define    RTL8367D_ACT26_PRIORITY_MASK    0x4
#define    RTL8367D_ACT26_SVID_OFFSET    1
#define    RTL8367D_ACT26_SVID_MASK    0x2
#define    RTL8367D_ACT26_CVID_OFFSET    0
#define    RTL8367D_ACT26_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL14    0x0622
#define    RTL8367D_OP29_NOT_OFFSET    14
#define    RTL8367D_OP29_NOT_MASK    0x4000
#define    RTL8367D_ACT29_GPIO_OFFSET    13
#define    RTL8367D_ACT29_GPIO_MASK    0x2000
#define    RTL8367D_ACT29_FORWARD_OFFSET    12
#define    RTL8367D_ACT29_FORWARD_MASK    0x1000
#define    RTL8367D_ACT29_POLICING_OFFSET    11
#define    RTL8367D_ACT29_POLICING_MASK    0x800
#define    RTL8367D_ACT29_PRIORITY_OFFSET    10
#define    RTL8367D_ACT29_PRIORITY_MASK    0x400
#define    RTL8367D_ACT29_SVID_OFFSET    9
#define    RTL8367D_ACT29_SVID_MASK    0x200
#define    RTL8367D_ACT29_CVID_OFFSET    8
#define    RTL8367D_ACT29_CVID_MASK    0x100
#define    RTL8367D_OP28_NOT_OFFSET    6
#define    RTL8367D_OP28_NOT_MASK    0x40
#define    RTL8367D_ACT28_GPIO_OFFSET    5
#define    RTL8367D_ACT28_GPIO_MASK    0x20
#define    RTL8367D_ACT28_FORWARD_OFFSET    4
#define    RTL8367D_ACT28_FORWARD_MASK    0x10
#define    RTL8367D_ACT28_POLICING_OFFSET    3
#define    RTL8367D_ACT28_POLICING_MASK    0x8
#define    RTL8367D_ACT28_PRIORITY_OFFSET    2
#define    RTL8367D_ACT28_PRIORITY_MASK    0x4
#define    RTL8367D_ACT28_SVID_OFFSET    1
#define    RTL8367D_ACT28_SVID_MASK    0x2
#define    RTL8367D_ACT28_CVID_OFFSET    0
#define    RTL8367D_ACT28_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL15    0x0623
#define    RTL8367D_OP31_NOT_OFFSET    14
#define    RTL8367D_OP31_NOT_MASK    0x4000
#define    RTL8367D_ACT31_GPIO_OFFSET    13
#define    RTL8367D_ACT31_GPIO_MASK    0x2000
#define    RTL8367D_ACT31_FORWARD_OFFSET    12
#define    RTL8367D_ACT31_FORWARD_MASK    0x1000
#define    RTL8367D_ACT31_POLICING_OFFSET    11
#define    RTL8367D_ACT31_POLICING_MASK    0x800
#define    RTL8367D_ACT31_PRIORITY_OFFSET    10
#define    RTL8367D_ACT31_PRIORITY_MASK    0x400
#define    RTL8367D_ACT31_SVID_OFFSET    9
#define    RTL8367D_ACT31_SVID_MASK    0x200
#define    RTL8367D_ACT31_CVID_OFFSET    8
#define    RTL8367D_ACT31_CVID_MASK    0x100
#define    RTL8367D_OP30_NOT_OFFSET    6
#define    RTL8367D_OP30_NOT_MASK    0x40
#define    RTL8367D_ACT30_GPIO_OFFSET    5
#define    RTL8367D_ACT30_GPIO_MASK    0x20
#define    RTL8367D_ACT30_FORWARD_OFFSET    4
#define    RTL8367D_ACT30_FORWARD_MASK    0x10
#define    RTL8367D_ACT30_POLICING_OFFSET    3
#define    RTL8367D_ACT30_POLICING_MASK    0x8
#define    RTL8367D_ACT30_PRIORITY_OFFSET    2
#define    RTL8367D_ACT30_PRIORITY_MASK    0x4
#define    RTL8367D_ACT30_SVID_OFFSET    1
#define    RTL8367D_ACT30_SVID_MASK    0x2
#define    RTL8367D_ACT30_CVID_OFFSET    0
#define    RTL8367D_ACT30_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL16    0x0624
#define    RTL8367D_OP33_NOT_OFFSET    14
#define    RTL8367D_OP33_NOT_MASK    0x4000
#define    RTL8367D_ACT33_GPIO_OFFSET    13
#define    RTL8367D_ACT33_GPIO_MASK    0x2000
#define    RTL8367D_ACT33_FORWARD_OFFSET    12
#define    RTL8367D_ACT33_FORWARD_MASK    0x1000
#define    RTL8367D_ACT33_POLICING_OFFSET    11
#define    RTL8367D_ACT33_POLICING_MASK    0x800
#define    RTL8367D_ACT33_PRIORITY_OFFSET    10
#define    RTL8367D_ACT33_PRIORITY_MASK    0x400
#define    RTL8367D_ACT33_SVID_OFFSET    9
#define    RTL8367D_ACT33_SVID_MASK    0x200
#define    RTL8367D_ACT33_CVID_OFFSET    8
#define    RTL8367D_ACT33_CVID_MASK    0x100
#define    RTL8367D_OP32_NOT_OFFSET    6
#define    RTL8367D_OP32_NOT_MASK    0x40
#define    RTL8367D_ACT32_GPIO_OFFSET    5
#define    RTL8367D_ACT32_GPIO_MASK    0x20
#define    RTL8367D_ACT32_FORWARD_OFFSET    4
#define    RTL8367D_ACT32_FORWARD_MASK    0x10
#define    RTL8367D_ACT32_POLICING_OFFSET    3
#define    RTL8367D_ACT32_POLICING_MASK    0x8
#define    RTL8367D_ACT32_PRIORITY_OFFSET    2
#define    RTL8367D_ACT32_PRIORITY_MASK    0x4
#define    RTL8367D_ACT32_SVID_OFFSET    1
#define    RTL8367D_ACT32_SVID_MASK    0x2
#define    RTL8367D_ACT32_CVID_OFFSET    0
#define    RTL8367D_ACT32_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL17    0x0625
#define    RTL8367D_OP35_NOT_OFFSET    14
#define    RTL8367D_OP35_NOT_MASK    0x4000
#define    RTL8367D_ACT35_GPIO_OFFSET    13
#define    RTL8367D_ACT35_GPIO_MASK    0x2000
#define    RTL8367D_ACT35_FORWARD_OFFSET    12
#define    RTL8367D_ACT35_FORWARD_MASK    0x1000
#define    RTL8367D_ACT35_POLICING_OFFSET    11
#define    RTL8367D_ACT35_POLICING_MASK    0x800
#define    RTL8367D_ACT35_PRIORITY_OFFSET    10
#define    RTL8367D_ACT35_PRIORITY_MASK    0x400
#define    RTL8367D_ACT35_SVID_OFFSET    9
#define    RTL8367D_ACT35_SVID_MASK    0x200
#define    RTL8367D_ACT35_CVID_OFFSET    8
#define    RTL8367D_ACT35_CVID_MASK    0x100
#define    RTL8367D_OP34_NOT_OFFSET    6
#define    RTL8367D_OP34_NOT_MASK    0x40
#define    RTL8367D_ACT34_GPIO_OFFSET    5
#define    RTL8367D_ACT34_GPIO_MASK    0x20
#define    RTL8367D_ACT34_FORWARD_OFFSET    4
#define    RTL8367D_ACT34_FORWARD_MASK    0x10
#define    RTL8367D_ACT34_POLICING_OFFSET    3
#define    RTL8367D_ACT34_POLICING_MASK    0x8
#define    RTL8367D_ACT34_PRIORITY_OFFSET    2
#define    RTL8367D_ACT34_PRIORITY_MASK    0x4
#define    RTL8367D_ACT34_SVID_OFFSET    1
#define    RTL8367D_ACT34_SVID_MASK    0x2
#define    RTL8367D_ACT34_CVID_OFFSET    0
#define    RTL8367D_ACT34_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL18    0x0626
#define    RTL8367D_OP37_NOT_OFFSET    14
#define    RTL8367D_OP37_NOT_MASK    0x4000
#define    RTL8367D_ACT37_GPIO_OFFSET    13
#define    RTL8367D_ACT37_GPIO_MASK    0x2000
#define    RTL8367D_ACT37_FORWARD_OFFSET    12
#define    RTL8367D_ACT37_FORWARD_MASK    0x1000
#define    RTL8367D_ACT37_POLICING_OFFSET    11
#define    RTL8367D_ACT37_POLICING_MASK    0x800
#define    RTL8367D_ACT37_PRIORITY_OFFSET    10
#define    RTL8367D_ACT37_PRIORITY_MASK    0x400
#define    RTL8367D_ACT37_SVID_OFFSET    9
#define    RTL8367D_ACT37_SVID_MASK    0x200
#define    RTL8367D_ACT37_CVID_OFFSET    8
#define    RTL8367D_ACT37_CVID_MASK    0x100
#define    RTL8367D_OP36_NOT_OFFSET    6
#define    RTL8367D_OP36_NOT_MASK    0x40
#define    RTL8367D_ACT36_GPIO_OFFSET    5
#define    RTL8367D_ACT36_GPIO_MASK    0x20
#define    RTL8367D_ACT36_FORWARD_OFFSET    4
#define    RTL8367D_ACT36_FORWARD_MASK    0x10
#define    RTL8367D_ACT36_POLICING_OFFSET    3
#define    RTL8367D_ACT36_POLICING_MASK    0x8
#define    RTL8367D_ACT36_PRIORITY_OFFSET    2
#define    RTL8367D_ACT36_PRIORITY_MASK    0x4
#define    RTL8367D_ACT36_SVID_OFFSET    1
#define    RTL8367D_ACT36_SVID_MASK    0x2
#define    RTL8367D_ACT36_CVID_OFFSET    0
#define    RTL8367D_ACT36_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL19    0x0627
#define    RTL8367D_OP39_NOT_OFFSET    14
#define    RTL8367D_OP39_NOT_MASK    0x4000
#define    RTL8367D_ACT39_GPIO_OFFSET    13
#define    RTL8367D_ACT39_GPIO_MASK    0x2000
#define    RTL8367D_ACT39_FORWARD_OFFSET    12
#define    RTL8367D_ACT39_FORWARD_MASK    0x1000
#define    RTL8367D_ACT39_POLICING_OFFSET    11
#define    RTL8367D_ACT39_POLICING_MASK    0x800
#define    RTL8367D_ACT39_PRIORITY_OFFSET    10
#define    RTL8367D_ACT39_PRIORITY_MASK    0x400
#define    RTL8367D_ACT39_SVID_OFFSET    9
#define    RTL8367D_ACT39_SVID_MASK    0x200
#define    RTL8367D_ACT39_CVID_OFFSET    8
#define    RTL8367D_ACT39_CVID_MASK    0x100
#define    RTL8367D_OP38_NOT_OFFSET    6
#define    RTL8367D_OP38_NOT_MASK    0x40
#define    RTL8367D_ACT38_GPIO_OFFSET    5
#define    RTL8367D_ACT38_GPIO_MASK    0x20
#define    RTL8367D_ACT38_FORWARD_OFFSET    4
#define    RTL8367D_ACT38_FORWARD_MASK    0x10
#define    RTL8367D_ACT38_POLICING_OFFSET    3
#define    RTL8367D_ACT38_POLICING_MASK    0x8
#define    RTL8367D_ACT38_PRIORITY_OFFSET    2
#define    RTL8367D_ACT38_PRIORITY_MASK    0x4
#define    RTL8367D_ACT38_SVID_OFFSET    1
#define    RTL8367D_ACT38_SVID_MASK    0x2
#define    RTL8367D_ACT38_CVID_OFFSET    0
#define    RTL8367D_ACT38_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL20    0x0628
#define    RTL8367D_OP41_NOT_OFFSET    14
#define    RTL8367D_OP41_NOT_MASK    0x4000
#define    RTL8367D_ACT41_GPIO_OFFSET    13
#define    RTL8367D_ACT41_GPIO_MASK    0x2000
#define    RTL8367D_ACT41_FORWARD_OFFSET    12
#define    RTL8367D_ACT41_FORWARD_MASK    0x1000
#define    RTL8367D_ACT41_POLICING_OFFSET    11
#define    RTL8367D_ACT41_POLICING_MASK    0x800
#define    RTL8367D_ACT41_PRIORITY_OFFSET    10
#define    RTL8367D_ACT41_PRIORITY_MASK    0x400
#define    RTL8367D_ACT41_SVID_OFFSET    9
#define    RTL8367D_ACT41_SVID_MASK    0x200
#define    RTL8367D_ACT41_CVID_OFFSET    8
#define    RTL8367D_ACT41_CVID_MASK    0x100
#define    RTL8367D_OP40_NOT_OFFSET    6
#define    RTL8367D_OP40_NOT_MASK    0x40
#define    RTL8367D_ACT40_GPIO_OFFSET    5
#define    RTL8367D_ACT40_GPIO_MASK    0x20
#define    RTL8367D_ACT40_FORWARD_OFFSET    4
#define    RTL8367D_ACT40_FORWARD_MASK    0x10
#define    RTL8367D_ACT40_POLICING_OFFSET    3
#define    RTL8367D_ACT40_POLICING_MASK    0x8
#define    RTL8367D_ACT40_PRIORITY_OFFSET    2
#define    RTL8367D_ACT40_PRIORITY_MASK    0x4
#define    RTL8367D_ACT40_SVID_OFFSET    1
#define    RTL8367D_ACT40_SVID_MASK    0x2
#define    RTL8367D_ACT40_CVID_OFFSET    0
#define    RTL8367D_ACT40_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL21    0x0629
#define    RTL8367D_OP43_NOT_OFFSET    14
#define    RTL8367D_OP43_NOT_MASK    0x4000
#define    RTL8367D_ACT43_GPIO_OFFSET    13
#define    RTL8367D_ACT43_GPIO_MASK    0x2000
#define    RTL8367D_ACT43_FORWARD_OFFSET    12
#define    RTL8367D_ACT43_FORWARD_MASK    0x1000
#define    RTL8367D_ACT43_POLICING_OFFSET    11
#define    RTL8367D_ACT43_POLICING_MASK    0x800
#define    RTL8367D_ACT43_PRIORITY_OFFSET    10
#define    RTL8367D_ACT43_PRIORITY_MASK    0x400
#define    RTL8367D_ACT43_SVID_OFFSET    9
#define    RTL8367D_ACT43_SVID_MASK    0x200
#define    RTL8367D_ACT43_CVID_OFFSET    8
#define    RTL8367D_ACT43_CVID_MASK    0x100
#define    RTL8367D_OP42_NOT_OFFSET    6
#define    RTL8367D_OP42_NOT_MASK    0x40
#define    RTL8367D_ACT42_GPIO_OFFSET    5
#define    RTL8367D_ACT42_GPIO_MASK    0x20
#define    RTL8367D_ACT42_FORWARD_OFFSET    4
#define    RTL8367D_ACT42_FORWARD_MASK    0x10
#define    RTL8367D_ACT42_POLICING_OFFSET    3
#define    RTL8367D_ACT42_POLICING_MASK    0x8
#define    RTL8367D_ACT42_PRIORITY_OFFSET    2
#define    RTL8367D_ACT42_PRIORITY_MASK    0x4
#define    RTL8367D_ACT42_SVID_OFFSET    1
#define    RTL8367D_ACT42_SVID_MASK    0x2
#define    RTL8367D_ACT42_CVID_OFFSET    0
#define    RTL8367D_ACT42_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL22    0x062a
#define    RTL8367D_OP45_NOT_OFFSET    14
#define    RTL8367D_OP45_NOT_MASK    0x4000
#define    RTL8367D_ACT45_GPIO_OFFSET    13
#define    RTL8367D_ACT45_GPIO_MASK    0x2000
#define    RTL8367D_ACT45_FORWARD_OFFSET    12
#define    RTL8367D_ACT45_FORWARD_MASK    0x1000
#define    RTL8367D_ACT45_POLICING_OFFSET    11
#define    RTL8367D_ACT45_POLICING_MASK    0x800
#define    RTL8367D_ACT45_PRIORITY_OFFSET    10
#define    RTL8367D_ACT45_PRIORITY_MASK    0x400
#define    RTL8367D_ACT45_SVID_OFFSET    9
#define    RTL8367D_ACT45_SVID_MASK    0x200
#define    RTL8367D_ACT45_CVID_OFFSET    8
#define    RTL8367D_ACT45_CVID_MASK    0x100
#define    RTL8367D_OP44_NOT_OFFSET    6
#define    RTL8367D_OP44_NOT_MASK    0x40
#define    RTL8367D_ACT44_GPIO_OFFSET    5
#define    RTL8367D_ACT44_GPIO_MASK    0x20
#define    RTL8367D_ACT44_FORWARD_OFFSET    4
#define    RTL8367D_ACT44_FORWARD_MASK    0x10
#define    RTL8367D_ACT44_POLICING_OFFSET    3
#define    RTL8367D_ACT44_POLICING_MASK    0x8
#define    RTL8367D_ACT44_PRIORITY_OFFSET    2
#define    RTL8367D_ACT44_PRIORITY_MASK    0x4
#define    RTL8367D_ACT44_SVID_OFFSET    1
#define    RTL8367D_ACT44_SVID_MASK    0x2
#define    RTL8367D_ACT44_CVID_OFFSET    0
#define    RTL8367D_ACT44_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL23    0x062b
#define    RTL8367D_OP47_NOT_OFFSET    14
#define    RTL8367D_OP47_NOT_MASK    0x4000
#define    RTL8367D_ACT47_GPIO_OFFSET    13
#define    RTL8367D_ACT47_GPIO_MASK    0x2000
#define    RTL8367D_ACT47_FORWARD_OFFSET    12
#define    RTL8367D_ACT47_FORWARD_MASK    0x1000
#define    RTL8367D_ACT47_POLICING_OFFSET    11
#define    RTL8367D_ACT47_POLICING_MASK    0x800
#define    RTL8367D_ACT47_PRIORITY_OFFSET    10
#define    RTL8367D_ACT47_PRIORITY_MASK    0x400
#define    RTL8367D_ACT47_SVID_OFFSET    9
#define    RTL8367D_ACT47_SVID_MASK    0x200
#define    RTL8367D_ACT47_CVID_OFFSET    8
#define    RTL8367D_ACT47_CVID_MASK    0x100
#define    RTL8367D_OP46_NOT_OFFSET    6
#define    RTL8367D_OP46_NOT_MASK    0x40
#define    RTL8367D_ACT46_GPIO_OFFSET    5
#define    RTL8367D_ACT46_GPIO_MASK    0x20
#define    RTL8367D_ACT46_FORWARD_OFFSET    4
#define    RTL8367D_ACT46_FORWARD_MASK    0x10
#define    RTL8367D_ACT46_POLICING_OFFSET    3
#define    RTL8367D_ACT46_POLICING_MASK    0x8
#define    RTL8367D_ACT46_PRIORITY_OFFSET    2
#define    RTL8367D_ACT46_PRIORITY_MASK    0x4
#define    RTL8367D_ACT46_SVID_OFFSET    1
#define    RTL8367D_ACT46_SVID_MASK    0x2
#define    RTL8367D_ACT46_CVID_OFFSET    0
#define    RTL8367D_ACT46_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL24    0x062c
#define    RTL8367D_OP49_NOT_OFFSET    14
#define    RTL8367D_OP49_NOT_MASK    0x4000
#define    RTL8367D_ACT49_GPIO_OFFSET    13
#define    RTL8367D_ACT49_GPIO_MASK    0x2000
#define    RTL8367D_ACT49_FORWARD_OFFSET    12
#define    RTL8367D_ACT49_FORWARD_MASK    0x1000
#define    RTL8367D_ACT49_POLICING_OFFSET    11
#define    RTL8367D_ACT49_POLICING_MASK    0x800
#define    RTL8367D_ACT49_PRIORITY_OFFSET    10
#define    RTL8367D_ACT49_PRIORITY_MASK    0x400
#define    RTL8367D_ACT49_SVID_OFFSET    9
#define    RTL8367D_ACT49_SVID_MASK    0x200
#define    RTL8367D_ACT49_CVID_OFFSET    8
#define    RTL8367D_ACT49_CVID_MASK    0x100
#define    RTL8367D_OP48_NOT_OFFSET    6
#define    RTL8367D_OP48_NOT_MASK    0x40
#define    RTL8367D_ACT48_GPIO_OFFSET    5
#define    RTL8367D_ACT48_GPIO_MASK    0x20
#define    RTL8367D_ACT48_FORWARD_OFFSET    4
#define    RTL8367D_ACT48_FORWARD_MASK    0x10
#define    RTL8367D_ACT48_POLICING_OFFSET    3
#define    RTL8367D_ACT48_POLICING_MASK    0x8
#define    RTL8367D_ACT48_PRIORITY_OFFSET    2
#define    RTL8367D_ACT48_PRIORITY_MASK    0x4
#define    RTL8367D_ACT48_SVID_OFFSET    1
#define    RTL8367D_ACT48_SVID_MASK    0x2
#define    RTL8367D_ACT48_CVID_OFFSET    0
#define    RTL8367D_ACT48_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL25    0x062d
#define    RTL8367D_OP51_NOT_OFFSET    14
#define    RTL8367D_OP51_NOT_MASK    0x4000
#define    RTL8367D_ACT51_GPIO_OFFSET    13
#define    RTL8367D_ACT51_GPIO_MASK    0x2000
#define    RTL8367D_ACT51_FORWARD_OFFSET    12
#define    RTL8367D_ACT51_FORWARD_MASK    0x1000
#define    RTL8367D_ACT51_POLICING_OFFSET    11
#define    RTL8367D_ACT51_POLICING_MASK    0x800
#define    RTL8367D_ACT51_PRIORITY_OFFSET    10
#define    RTL8367D_ACT51_PRIORITY_MASK    0x400
#define    RTL8367D_ACT51_SVID_OFFSET    9
#define    RTL8367D_ACT51_SVID_MASK    0x200
#define    RTL8367D_ACT51_CVID_OFFSET    8
#define    RTL8367D_ACT51_CVID_MASK    0x100
#define    RTL8367D_OP50_NOT_OFFSET    6
#define    RTL8367D_OP50_NOT_MASK    0x40
#define    RTL8367D_ACT50_GPIO_OFFSET    5
#define    RTL8367D_ACT50_GPIO_MASK    0x20
#define    RTL8367D_ACT50_FORWARD_OFFSET    4
#define    RTL8367D_ACT50_FORWARD_MASK    0x10
#define    RTL8367D_ACT50_POLICING_OFFSET    3
#define    RTL8367D_ACT50_POLICING_MASK    0x8
#define    RTL8367D_ACT50_PRIORITY_OFFSET    2
#define    RTL8367D_ACT50_PRIORITY_MASK    0x4
#define    RTL8367D_ACT50_SVID_OFFSET    1
#define    RTL8367D_ACT50_SVID_MASK    0x2
#define    RTL8367D_ACT50_CVID_OFFSET    0
#define    RTL8367D_ACT50_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL26    0x062e
#define    RTL8367D_OP53_NOT_OFFSET    14
#define    RTL8367D_OP53_NOT_MASK    0x4000
#define    RTL8367D_ACT53_GPIO_OFFSET    13
#define    RTL8367D_ACT53_GPIO_MASK    0x2000
#define    RTL8367D_ACT53_FORWARD_OFFSET    12
#define    RTL8367D_ACT53_FORWARD_MASK    0x1000
#define    RTL8367D_ACT53_POLICING_OFFSET    11
#define    RTL8367D_ACT53_POLICING_MASK    0x800
#define    RTL8367D_ACT53_PRIORITY_OFFSET    10
#define    RTL8367D_ACT53_PRIORITY_MASK    0x400
#define    RTL8367D_ACT53_SVID_OFFSET    9
#define    RTL8367D_ACT53_SVID_MASK    0x200
#define    RTL8367D_ACT53_CVID_OFFSET    8
#define    RTL8367D_ACT53_CVID_MASK    0x100
#define    RTL8367D_OP52_NOT_OFFSET    6
#define    RTL8367D_OP52_NOT_MASK    0x40
#define    RTL8367D_ACT52_GPIO_OFFSET    5
#define    RTL8367D_ACT52_GPIO_MASK    0x20
#define    RTL8367D_ACT52_FORWARD_OFFSET    4
#define    RTL8367D_ACT52_FORWARD_MASK    0x10
#define    RTL8367D_ACT52_POLICING_OFFSET    3
#define    RTL8367D_ACT52_POLICING_MASK    0x8
#define    RTL8367D_ACT52_PRIORITY_OFFSET    2
#define    RTL8367D_ACT52_PRIORITY_MASK    0x4
#define    RTL8367D_ACT52_SVID_OFFSET    1
#define    RTL8367D_ACT52_SVID_MASK    0x2
#define    RTL8367D_ACT52_CVID_OFFSET    0
#define    RTL8367D_ACT52_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL27    0x062f
#define    RTL8367D_OP55_NOT_OFFSET    14
#define    RTL8367D_OP55_NOT_MASK    0x4000
#define    RTL8367D_ACT55_GPIO_OFFSET    13
#define    RTL8367D_ACT55_GPIO_MASK    0x2000
#define    RTL8367D_ACT55_FORWARD_OFFSET    12
#define    RTL8367D_ACT55_FORWARD_MASK    0x1000
#define    RTL8367D_ACT55_POLICING_OFFSET    11
#define    RTL8367D_ACT55_POLICING_MASK    0x800
#define    RTL8367D_ACT55_PRIORITY_OFFSET    10
#define    RTL8367D_ACT55_PRIORITY_MASK    0x400
#define    RTL8367D_ACT55_SVID_OFFSET    9
#define    RTL8367D_ACT55_SVID_MASK    0x200
#define    RTL8367D_ACT55_CVID_OFFSET    8
#define    RTL8367D_ACT55_CVID_MASK    0x100
#define    RTL8367D_OP54_NOT_OFFSET    6
#define    RTL8367D_OP54_NOT_MASK    0x40
#define    RTL8367D_ACT54_GPIO_OFFSET    5
#define    RTL8367D_ACT54_GPIO_MASK    0x20
#define    RTL8367D_ACT54_FORWARD_OFFSET    4
#define    RTL8367D_ACT54_FORWARD_MASK    0x10
#define    RTL8367D_ACT54_POLICING_OFFSET    3
#define    RTL8367D_ACT54_POLICING_MASK    0x8
#define    RTL8367D_ACT54_PRIORITY_OFFSET    2
#define    RTL8367D_ACT54_PRIORITY_MASK    0x4
#define    RTL8367D_ACT54_SVID_OFFSET    1
#define    RTL8367D_ACT54_SVID_MASK    0x2
#define    RTL8367D_ACT54_CVID_OFFSET    0
#define    RTL8367D_ACT54_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL28    0x0630
#define    RTL8367D_OP57_NOT_OFFSET    14
#define    RTL8367D_OP57_NOT_MASK    0x4000
#define    RTL8367D_ACT57_GPIO_OFFSET    13
#define    RTL8367D_ACT57_GPIO_MASK    0x2000
#define    RTL8367D_ACT57_FORWARD_OFFSET    12
#define    RTL8367D_ACT57_FORWARD_MASK    0x1000
#define    RTL8367D_ACT57_POLICING_OFFSET    11
#define    RTL8367D_ACT57_POLICING_MASK    0x800
#define    RTL8367D_ACT57_PRIORITY_OFFSET    10
#define    RTL8367D_ACT57_PRIORITY_MASK    0x400
#define    RTL8367D_ACT57_SVID_OFFSET    9
#define    RTL8367D_ACT57_SVID_MASK    0x200
#define    RTL8367D_ACT57_CVID_OFFSET    8
#define    RTL8367D_ACT57_CVID_MASK    0x100
#define    RTL8367D_OP56_NOT_OFFSET    6
#define    RTL8367D_OP56_NOT_MASK    0x40
#define    RTL8367D_ACT56_GPIO_OFFSET    5
#define    RTL8367D_ACT56_GPIO_MASK    0x20
#define    RTL8367D_ACT56_FORWARD_OFFSET    4
#define    RTL8367D_ACT56_FORWARD_MASK    0x10
#define    RTL8367D_ACT56_POLICING_OFFSET    3
#define    RTL8367D_ACT56_POLICING_MASK    0x8
#define    RTL8367D_ACT56_PRIORITY_OFFSET    2
#define    RTL8367D_ACT56_PRIORITY_MASK    0x4
#define    RTL8367D_ACT56_SVID_OFFSET    1
#define    RTL8367D_ACT56_SVID_MASK    0x2
#define    RTL8367D_ACT56_CVID_OFFSET    0
#define    RTL8367D_ACT56_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL29    0x0631
#define    RTL8367D_OP59_NOT_OFFSET    14
#define    RTL8367D_OP59_NOT_MASK    0x4000
#define    RTL8367D_ACT59_GPIO_OFFSET    13
#define    RTL8367D_ACT59_GPIO_MASK    0x2000
#define    RTL8367D_ACT59_FORWARD_OFFSET    12
#define    RTL8367D_ACT59_FORWARD_MASK    0x1000
#define    RTL8367D_ACT59_POLICING_OFFSET    11
#define    RTL8367D_ACT59_POLICING_MASK    0x800
#define    RTL8367D_ACT59_PRIORITY_OFFSET    10
#define    RTL8367D_ACT59_PRIORITY_MASK    0x400
#define    RTL8367D_ACT59_SVID_OFFSET    9
#define    RTL8367D_ACT59_SVID_MASK    0x200
#define    RTL8367D_ACT59_CVID_OFFSET    8
#define    RTL8367D_ACT59_CVID_MASK    0x100
#define    RTL8367D_OP58_NOT_OFFSET    6
#define    RTL8367D_OP58_NOT_MASK    0x40
#define    RTL8367D_ACT58_GPIO_OFFSET    5
#define    RTL8367D_ACT58_GPIO_MASK    0x20
#define    RTL8367D_ACT58_FORWARD_OFFSET    4
#define    RTL8367D_ACT58_FORWARD_MASK    0x10
#define    RTL8367D_ACT58_POLICING_OFFSET    3
#define    RTL8367D_ACT58_POLICING_MASK    0x8
#define    RTL8367D_ACT58_PRIORITY_OFFSET    2
#define    RTL8367D_ACT58_PRIORITY_MASK    0x4
#define    RTL8367D_ACT58_SVID_OFFSET    1
#define    RTL8367D_ACT58_SVID_MASK    0x2
#define    RTL8367D_ACT58_CVID_OFFSET    0
#define    RTL8367D_ACT58_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL30    0x0632
#define    RTL8367D_OP61_NOT_OFFSET    14
#define    RTL8367D_OP61_NOT_MASK    0x4000
#define    RTL8367D_ACT61_GPIO_OFFSET    13
#define    RTL8367D_ACT61_GPIO_MASK    0x2000
#define    RTL8367D_ACT61_FORWARD_OFFSET    12
#define    RTL8367D_ACT61_FORWARD_MASK    0x1000
#define    RTL8367D_ACT61_POLICING_OFFSET    11
#define    RTL8367D_ACT61_POLICING_MASK    0x800
#define    RTL8367D_ACT61_PRIORITY_OFFSET    10
#define    RTL8367D_ACT61_PRIORITY_MASK    0x400
#define    RTL8367D_ACT61_SVID_OFFSET    9
#define    RTL8367D_ACT61_SVID_MASK    0x200
#define    RTL8367D_ACT61_CVID_OFFSET    8
#define    RTL8367D_ACT61_CVID_MASK    0x100
#define    RTL8367D_OP60_NOT_OFFSET    6
#define    RTL8367D_OP60_NOT_MASK    0x40
#define    RTL8367D_ACT60_GPIO_OFFSET    5
#define    RTL8367D_ACT60_GPIO_MASK    0x20
#define    RTL8367D_ACT60_FORWARD_OFFSET    4
#define    RTL8367D_ACT60_FORWARD_MASK    0x10
#define    RTL8367D_ACT60_POLICING_OFFSET    3
#define    RTL8367D_ACT60_POLICING_MASK    0x8
#define    RTL8367D_ACT60_PRIORITY_OFFSET    2
#define    RTL8367D_ACT60_PRIORITY_MASK    0x4
#define    RTL8367D_ACT60_SVID_OFFSET    1
#define    RTL8367D_ACT60_SVID_MASK    0x2
#define    RTL8367D_ACT60_CVID_OFFSET    0
#define    RTL8367D_ACT60_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_ACTION_CTRL31    0x0633
#define    RTL8367D_OP63_NOT_OFFSET    14
#define    RTL8367D_OP63_NOT_MASK    0x4000
#define    RTL8367D_ACT63_GPIO_OFFSET    13
#define    RTL8367D_ACT63_GPIO_MASK    0x2000
#define    RTL8367D_ACT63_FORWARD_OFFSET    12
#define    RTL8367D_ACT63_FORWARD_MASK    0x1000
#define    RTL8367D_ACT63_POLICING_OFFSET    11
#define    RTL8367D_ACT63_POLICING_MASK    0x800
#define    RTL8367D_ACT63_PRIORITY_OFFSET    10
#define    RTL8367D_ACT63_PRIORITY_MASK    0x400
#define    RTL8367D_ACT63_SVID_OFFSET    9
#define    RTL8367D_ACT63_SVID_MASK    0x200
#define    RTL8367D_ACT63_CVID_OFFSET    8
#define    RTL8367D_ACT63_CVID_MASK    0x100
#define    RTL8367D_OP62_NOT_OFFSET    6
#define    RTL8367D_OP62_NOT_MASK    0x40
#define    RTL8367D_ACT62_GPIO_OFFSET    5
#define    RTL8367D_ACT62_GPIO_MASK    0x20
#define    RTL8367D_ACT62_FORWARD_OFFSET    4
#define    RTL8367D_ACT62_FORWARD_MASK    0x10
#define    RTL8367D_ACT62_POLICING_OFFSET    3
#define    RTL8367D_ACT62_POLICING_MASK    0x8
#define    RTL8367D_ACT62_PRIORITY_OFFSET    2
#define    RTL8367D_ACT62_PRIORITY_MASK    0x4
#define    RTL8367D_ACT62_SVID_OFFSET    1
#define    RTL8367D_ACT62_SVID_MASK    0x2
#define    RTL8367D_ACT62_CVID_OFFSET    0
#define    RTL8367D_ACT62_CVID_MASK    0x1

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL0    0x0685

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL1    0x0686

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL2    0x0687

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL3    0x0688

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL4    0x0689
#define    RTL8367D_ACL_IP_RANGE_ENTRY0_CTRL4_OFFSET    0
#define    RTL8367D_ACL_IP_RANGE_ENTRY0_CTRL4_MASK    0x7

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY1_CTRL0    0x068a

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY1_CTRL1    0x068b

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY1_CTRL2    0x068c

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY1_CTRL3    0x068d

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY1_CTRL4    0x068e
#define    RTL8367D_ACL_IP_RANGE_ENTRY1_CTRL4_OFFSET    0
#define    RTL8367D_ACL_IP_RANGE_ENTRY1_CTRL4_MASK    0x7

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY2_CTRL0    0x068f

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY2_CTRL1    0x0690

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY2_CTRL2    0x0691

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY2_CTRL3    0x0692

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY2_CTRL4    0x0693
#define    RTL8367D_ACL_IP_RANGE_ENTRY2_CTRL4_OFFSET    0
#define    RTL8367D_ACL_IP_RANGE_ENTRY2_CTRL4_MASK    0x7

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY3_CTRL0    0x0694

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY3_CTRL1    0x0695

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY3_CTRL2    0x0696

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY3_CTRL3    0x0697

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY3_CTRL4    0x0698
#define    RTL8367D_ACL_IP_RANGE_ENTRY3_CTRL4_OFFSET    0
#define    RTL8367D_ACL_IP_RANGE_ENTRY3_CTRL4_MASK    0x7

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY4_CTRL0    0x0699

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY4_CTRL1    0x069a

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY4_CTRL2    0x069b

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY4_CTRL3    0x069c

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY4_CTRL4    0x069d
#define    RTL8367D_ACL_IP_RANGE_ENTRY4_CTRL4_OFFSET    0
#define    RTL8367D_ACL_IP_RANGE_ENTRY4_CTRL4_MASK    0x7

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY5_CTRL0    0x069e

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY5_CTRL1    0x069f

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY5_CTRL2    0x06a0

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY5_CTRL3    0x06a1

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY5_CTRL4    0x06a2
#define    RTL8367D_ACL_IP_RANGE_ENTRY5_CTRL4_OFFSET    0
#define    RTL8367D_ACL_IP_RANGE_ENTRY5_CTRL4_MASK    0x7

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY6_CTRL0    0x06a3

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY6_CTRL1    0x06a4

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY6_CTRL2    0x06a5

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY6_CTRL3    0x06a6

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY6_CTRL4    0x06a7
#define    RTL8367D_ACL_IP_RANGE_ENTRY6_CTRL4_OFFSET    0
#define    RTL8367D_ACL_IP_RANGE_ENTRY6_CTRL4_MASK    0x7

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY7_CTRL0    0x06a8

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY7_CTRL1    0x06a9

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY7_CTRL2    0x06aa

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY7_CTRL3    0x06ab

#define    RTL8367D_REG_ACL_IP_RANGE_ENTRY7_CTRL4    0x06ac
#define    RTL8367D_ACL_IP_RANGE_ENTRY7_CTRL4_OFFSET    0
#define    RTL8367D_ACL_IP_RANGE_ENTRY7_CTRL4_MASK    0x7

#define    RTL8367D_REG_ACL_ENABLE    0x06d5
#define    RTL8367D_PORT7_ENABLE_OFFSET    7
#define    RTL8367D_PORT7_ENABLE_MASK    0x80
#define    RTL8367D_PORT6_ENABLE_OFFSET    6
#define    RTL8367D_PORT6_ENABLE_MASK    0x40
#define    RTL8367D_PORT5_ENABLE_OFFSET    5
#define    RTL8367D_PORT5_ENABLE_MASK    0x20
#define    RTL8367D_PORT4_ENABLE_OFFSET    4
#define    RTL8367D_PORT4_ENABLE_MASK    0x10
#define    RTL8367D_PORT3_ENABLE_OFFSET    3
#define    RTL8367D_PORT3_ENABLE_MASK    0x8
#define    RTL8367D_PORT2_ENABLE_OFFSET    2
#define    RTL8367D_PORT2_ENABLE_MASK    0x4
#define    RTL8367D_PORT1_ENABLE_OFFSET    1
#define    RTL8367D_PORT1_ENABLE_MASK    0x2
#define    RTL8367D_PORT0_ENABLE_OFFSET    0
#define    RTL8367D_PORT0_ENABLE_MASK    0x1

#define    RTL8367D_REG_ACL_UNMATCH_PERMIT    0x06d6
#define    RTL8367D_PORT7_PERMIT_OFFSET    7
#define    RTL8367D_PORT7_PERMIT_MASK    0x80
#define    RTL8367D_PORT6_PERMIT_OFFSET    6
#define    RTL8367D_PORT6_PERMIT_MASK    0x40
#define    RTL8367D_PORT5_PERMIT_OFFSET    5
#define    RTL8367D_PORT5_PERMIT_MASK    0x20
#define    RTL8367D_PORT4_PERMIT_OFFSET    4
#define    RTL8367D_PORT4_PERMIT_MASK    0x10
#define    RTL8367D_PORT3_PERMIT_OFFSET    3
#define    RTL8367D_PORT3_PERMIT_MASK    0x8
#define    RTL8367D_PORT2_PERMIT_OFFSET    2
#define    RTL8367D_PORT2_PERMIT_MASK    0x4
#define    RTL8367D_PORT1_PERMIT_OFFSET    1
#define    RTL8367D_PORT1_PERMIT_MASK    0x2
#define    RTL8367D_PORT0_PERMIT_OFFSET    0
#define    RTL8367D_PORT0_PERMIT_MASK    0x1

#define    RTL8367D_REG_ACL_RESET_CFG    0x06d9
#define    RTL8367D_ACL_RESET_CFG_OFFSET    0
#define    RTL8367D_ACL_RESET_CFG_MASK    0x1

#define    RTL8367D_REG_ACL_REASON_01    0x06E8
#define    RTL8367D_ACL_ACT_1_OFFSET    8
#define    RTL8367D_ACL_ACT_1_MASK    0xFF00
#define    RTL8367D_ACL_ACT_0_OFFSET    0
#define    RTL8367D_ACL_ACT_0_MASK    0xFF

#define    RTL8367D_REG_ACL_REASON_23    0x06E9
#define    RTL8367D_ACL_ACT_3_OFFSET    8
#define    RTL8367D_ACL_ACT_3_MASK    0xFF00
#define    RTL8367D_ACL_ACT_2_OFFSET    0
#define    RTL8367D_ACL_ACT_2_MASK    0xFF

#define    RTL8367D_REG_ACL_REASON_45    0x06EA
#define    RTL8367D_ACL_ACT_5_OFFSET    8
#define    RTL8367D_ACL_ACT_5_MASK    0xFF00
#define    RTL8367D_ACL_ACT_4_OFFSET    0
#define    RTL8367D_ACL_ACT_4_MASK    0xFF

/* (16'h0700)cvlan_reg */

#define    RTL8367D_REG_VLAN_PVID_CTRL0    0x0700
#define    RTL8367D_VLAN_PVID_CTRL0_OFFSET    0
#define    RTL8367D_VLAN_PVID_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_VLAN_PVID_CTRL1    0x0701
#define    RTL8367D_VLAN_PVID_CTRL1_OFFSET    0
#define    RTL8367D_VLAN_PVID_CTRL1_MASK    0xFFF

#define    RTL8367D_REG_VLAN_PVID_CTRL2    0x0702
#define    RTL8367D_VLAN_PVID_CTRL2_OFFSET    0
#define    RTL8367D_VLAN_PVID_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_VLAN_PVID_CTRL3    0x0703
#define    RTL8367D_VLAN_PVID_CTRL3_OFFSET    0
#define    RTL8367D_VLAN_PVID_CTRL3_MASK    0xFFF

#define    RTL8367D_REG_VLAN_PVID_CTRL4    0x0704
#define    RTL8367D_VLAN_PVID_CTRL4_OFFSET    0
#define    RTL8367D_VLAN_PVID_CTRL4_MASK    0xFFF

#define    RTL8367D_REG_VLAN_PVID_CTRL5    0x0705
#define    RTL8367D_VLAN_PVID_CTRL5_OFFSET    0
#define    RTL8367D_VLAN_PVID_CTRL5_MASK    0xFFF

#define    RTL8367D_REG_VLAN_PVID_CTRL6    0x0706
#define    RTL8367D_VLAN_PVID_CTRL6_OFFSET    0
#define    RTL8367D_VLAN_PVID_CTRL6_MASK    0xFFF

#define    RTL8367D_REG_VLAN_PVID_CTRL7    0x0707
#define    RTL8367D_VLAN_PVID_CTRL7_OFFSET    0
#define    RTL8367D_VLAN_PVID_CTRL7_MASK    0xFFF

#define    RTL8367D_REG_VLAN_CTRL    0x07a8
#define    RTL8367D_VLAN_CTRL_OFFSET    0
#define    RTL8367D_VLAN_CTRL_MASK    0x1

#define    RTL8367D_REG_VLAN_INGRESS    0x07a9
#define    RTL8367D_VLAN_INGRESS_OFFSET    0
#define    RTL8367D_VLAN_INGRESS_MASK    0xFF

#define    RTL8367D_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0    0x07aa
#define    RTL8367D_PORT7_FRAME_TYPE_OFFSET    14
#define    RTL8367D_PORT7_FRAME_TYPE_MASK    0xC000
#define    RTL8367D_PORT6_FRAME_TYPE_OFFSET    12
#define    RTL8367D_PORT6_FRAME_TYPE_MASK    0x3000
#define    RTL8367D_PORT5_FRAME_TYPE_OFFSET    10
#define    RTL8367D_PORT5_FRAME_TYPE_MASK    0xC00
#define    RTL8367D_PORT4_FRAME_TYPE_OFFSET    8
#define    RTL8367D_PORT4_FRAME_TYPE_MASK    0x300
#define    RTL8367D_PORT3_FRAME_TYPE_OFFSET    6
#define    RTL8367D_PORT3_FRAME_TYPE_MASK    0xC0
#define    RTL8367D_PORT2_FRAME_TYPE_OFFSET    4
#define    RTL8367D_PORT2_FRAME_TYPE_MASK    0x30
#define    RTL8367D_PORT1_FRAME_TYPE_OFFSET    2
#define    RTL8367D_PORT1_FRAME_TYPE_MASK    0xC
#define    RTL8367D_PORT0_FRAME_TYPE_OFFSET    0
#define    RTL8367D_PORT0_FRAME_TYPE_MASK    0x3

#define    RTL8367D_REG_PORT_PBFIDEN    0x07ac
#define    RTL8367D_PORT_PBFIDEN_OFFSET    0
#define    RTL8367D_PORT_PBFIDEN_MASK    0xFF

#define    RTL8367D_REG_PORT0_PBFID    0x07ad
#define    RTL8367D_PORT0_PBFID_OFFSET    0
#define    RTL8367D_PORT0_PBFID_MASK    0x3

#define    RTL8367D_REG_PORT1_PBFID    0x07ae
#define    RTL8367D_PORT1_PBFID_OFFSET    0
#define    RTL8367D_PORT1_PBFID_MASK    0x3

#define    RTL8367D_REG_PORT2_PBFID    0x07af
#define    RTL8367D_PORT2_PBFID_OFFSET    0
#define    RTL8367D_PORT2_PBFID_MASK    0x3

#define    RTL8367D_REG_PORT3_PBFID    0x07b0
#define    RTL8367D_PORT3_PBFID_OFFSET    0
#define    RTL8367D_PORT3_PBFID_MASK    0x3

#define    RTL8367D_REG_PORT4_PBFID    0x07b1
#define    RTL8367D_PORT4_PBFID_OFFSET    0
#define    RTL8367D_PORT4_PBFID_MASK    0x3

#define    RTL8367D_REG_PORT5_PBFID    0x07b2
#define    RTL8367D_PORT5_PBFID_OFFSET    0
#define    RTL8367D_PORT5_PBFID_MASK    0x3

#define    RTL8367D_REG_PORT6_PBFID    0x07b3
#define    RTL8367D_PORT6_PBFID_OFFSET    0
#define    RTL8367D_PORT6_PBFID_MASK    0x3

#define    RTL8367D_REG_PORT7_PBFID    0x07b4
#define    RTL8367D_PORT7_PBFID_OFFSET    0
#define    RTL8367D_PORT7_PBFID_MASK    0x3

#define    RTL8367D_REG_VLAN_EXT_CTRL    0x07b5
#define    RTL8367D_VLAN_1P_REMARK_BYPASS_REALKEEP_OFFSET    2
#define    RTL8367D_VLAN_1P_REMARK_BYPASS_REALKEEP_MASK    0x4
#define    RTL8367D_VLAN_VID4095_TYPE_OFFSET    1
#define    RTL8367D_VLAN_VID4095_TYPE_MASK    0x2
#define    RTL8367D_VLAN_VID0_TYPE_OFFSET    0
#define    RTL8367D_VLAN_VID0_TYPE_MASK    0x1

#define    RTL8367D_REG_VLAN_EXT_CTRL2    0x07b6
#define    RTL8367D_VLAN_EXT_CTRL2_OFFSET    0
#define    RTL8367D_VLAN_EXT_CTRL2_MASK    0x1

#define    RTL8367D_REG_CVL_BISD_CTRL0    0x0780
#define    RTL8367D_CVL_FRCTL_OFFSET    14
#define    RTL8367D_CVL_FRCTL_MASK    0x4000
#define    RTL8367D_CVL_TGL_OFFSET    13
#define    RTL8367D_CVL_TGL_MASK    0x2000
#define    RTL8367D_CVL_WR_OFFSET    12
#define    RTL8367D_CVL_WR_MASK    0x1000
#define    RTL8367D_CVL_ADR_OFFSET    0
#define    RTL8367D_CVL_ADR_MASK    0xFFF

#define    RTL8367D_REG_CVL_BISD_CTRL1    0x0781

#define    RTL8367D_REG_CVL_BISD_CTRL2    0x0782

#define    RTL8367D_REG_CVL_BISD_CTRL3    0x0783
#define    RTL8367D_CVL_BISD_EN_OFFSET    3
#define    RTL8367D_CVL_BISD_EN_MASK    0x8
#define    RTL8367D_CVL_CONS_VAL_OFFSET    2
#define    RTL8367D_CVL_CONS_VAL_MASK    0x4
#define    RTL8367D_CVL_CONS_ACS_OFFSET    1
#define    RTL8367D_CVL_CONS_ACS_MASK    0x2
#define    RTL8367D_CVL_SEL16BNK_OFFSET    0
#define    RTL8367D_CVL_SEL16BNK_MASK    0x1

#define    RTL8367D_REG_CVL_BISD_CTRL4    0x0784

/* (16'h0800)dpm_reg */

#define    RTL8367D_REG_RMA_CTRL00    0x0800
#define    RTL8367D_RMA_CTRL00_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL00_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL00_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL00_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_TRAP_PRIORITY_OFFSET    3
#define    RTL8367D_TRAP_PRIORITY_MASK    0x38
#define    RTL8367D_RMA_CTRL00_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL00_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL00_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL00_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL00_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL00_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL01    0x0801
#define    RTL8367D_RMA_CTRL01_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL01_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL01_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL01_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL01_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL01_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL01_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL01_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL01_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL01_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL02    0x0802
#define    RTL8367D_RMA_CTRL02_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL02_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL02_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL02_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL02_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL02_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL02_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL02_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL02_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL02_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL03    0x0803
#define    RTL8367D_RMA_CTRL03_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL03_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL03_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL03_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL03_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL03_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL03_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL03_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL03_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL03_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL04    0x0804
#define    RTL8367D_RMA_CTRL04_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL04_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL04_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL04_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL04_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL04_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL04_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL04_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL04_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL04_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL08    0x0808
#define    RTL8367D_RMA_CTRL08_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL08_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL08_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL08_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL08_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL08_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL08_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL08_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL08_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL08_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL0D    0x080d
#define    RTL8367D_RMA_CTRL0D_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL0D_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL0D_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL0D_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL0D_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL0D_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL0D_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL0D_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL0D_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL0D_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL0E    0x080e
#define    RTL8367D_RMA_CTRL0E_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL0E_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL0E_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL0E_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL0E_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL0E_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL0E_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL0E_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL0E_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL0E_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL10    0x0810
#define    RTL8367D_RMA_CTRL10_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL10_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL10_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL10_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL10_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL10_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL10_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL10_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL10_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL10_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL11    0x0811
#define    RTL8367D_RMA_CTRL11_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL11_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL11_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL11_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL11_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL11_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL11_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL11_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL11_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL11_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL12    0x0812
#define    RTL8367D_RMA_CTRL12_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL12_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL12_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL12_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL12_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL12_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL12_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL12_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL12_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL12_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL13    0x0813
#define    RTL8367D_RMA_CTRL13_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL13_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL13_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL13_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL13_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL13_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL13_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL13_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL13_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL13_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL18    0x0818
#define    RTL8367D_RMA_CTRL18_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL18_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL18_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL18_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL18_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL18_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL18_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL18_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL18_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL18_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL1A    0x081a
#define    RTL8367D_RMA_CTRL1A_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL1A_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL1A_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL1A_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL1A_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL1A_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL1A_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL1A_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL1A_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL1A_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL20    0x0820
#define    RTL8367D_RMA_CTRL20_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL20_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL20_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL20_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL20_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL20_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL20_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL20_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL20_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL20_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL21    0x0821
#define    RTL8367D_RMA_CTRL21_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL21_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL21_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL21_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL21_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL21_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL21_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL21_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL21_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL21_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL22    0x0822
#define    RTL8367D_RMA_CTRL22_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL22_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL22_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL22_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL22_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL22_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL22_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL22_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL22_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL22_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL_CDP    0x0830
#define    RTL8367D_RMA_CTRL_CDP_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL_CDP_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL_CDP_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL_CDP_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL_CDP_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL_CDP_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL_CDP_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL_CDP_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL_CDP_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL_CDP_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL_CSSTP    0x0831
#define    RTL8367D_RMA_CTRL_CSSTP_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL_CSSTP_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL_CSSTP_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL_CSSTP_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL_CSSTP_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL_CSSTP_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL_CSSTP_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL_CSSTP_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_CTRL_LLDP    0x0832
#define    RTL8367D_RMA_CTRL_LLDP_OPERATION_OFFSET    7
#define    RTL8367D_RMA_CTRL_LLDP_OPERATION_MASK    0x180
#define    RTL8367D_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_OFFSET    6
#define    RTL8367D_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_MASK    0x40
#define    RTL8367D_RMA_CTRL_LLDP_KEEP_FORMAT_OFFSET    2
#define    RTL8367D_RMA_CTRL_LLDP_KEEP_FORMAT_MASK    0x4
#define    RTL8367D_RMA_CTRL_LLDP_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_RMA_CTRL_LLDP_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_RMA_CTRL_LLDP_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_RMA_CTRL_LLDP_PORTISO_LEAKY_MASK    0x1

#define    RTL8367D_REG_RMA_LLDP_EN    0x0833
#define    RTL8367D_RMA_LLDP_EN_OFFSET    0
#define    RTL8367D_RMA_LLDP_EN_MASK    0x1

#define    RTL8367D_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0    0x0865
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_OFFSET    12
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_MASK    0x7000
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_OFFSET    8
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_MASK    0x700
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_OFFSET    4
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_MASK    0x70
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_OFFSET    0
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_MASK    0x7

#define    RTL8367D_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL1    0x0866
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_OFFSET    12
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_MASK    0x7000
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_OFFSET    8
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_MASK    0x700
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_OFFSET    4
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_MASK    0x70
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_OFFSET    0
#define    RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL0    0x0867
#define    RTL8367D_DSCP3_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP3_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP2_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP2_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP1_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP1_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP0_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP0_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL1    0x0868
#define    RTL8367D_DSCP7_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP7_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP6_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP6_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP5_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP5_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP4_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP4_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL2    0x0869
#define    RTL8367D_DSCP11_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP11_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP10_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP10_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP9_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP9_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP8_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP8_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL3    0x086a
#define    RTL8367D_DSCP15_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP15_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP14_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP14_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP13_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP13_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP12_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP12_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL4    0x086b
#define    RTL8367D_DSCP19_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP19_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP18_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP18_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP17_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP17_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP16_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP16_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL5    0x086c
#define    RTL8367D_DSCP23_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP23_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP22_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP22_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP21_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP21_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP20_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP20_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL6    0x086d
#define    RTL8367D_DSCP27_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP27_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP26_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP26_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP25_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP25_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP24_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP24_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL7    0x086e
#define    RTL8367D_DSCP31_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP31_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP30_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP30_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP29_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP29_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP28_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP28_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL8    0x086f
#define    RTL8367D_DSCP35_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP35_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP34_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP34_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP33_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP33_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP32_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP32_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL9    0x0870
#define    RTL8367D_DSCP39_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP39_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP38_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP38_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP37_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP37_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP36_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP36_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL10    0x0871
#define    RTL8367D_DSCP43_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP43_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP42_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP42_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP41_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP41_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP40_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP40_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL11    0x0872
#define    RTL8367D_DSCP47_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP47_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP46_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP46_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP45_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP45_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP44_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP44_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL12    0x0873
#define    RTL8367D_DSCP51_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP51_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP50_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP50_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP49_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP49_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP48_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP48_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL13    0x0874
#define    RTL8367D_DSCP55_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP55_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP54_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP54_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP53_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP53_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP52_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP52_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL14    0x0875
#define    RTL8367D_DSCP59_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP59_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP58_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP58_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP57_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP57_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP56_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP56_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL15    0x0876
#define    RTL8367D_DSCP63_PRIORITY_OFFSET    12
#define    RTL8367D_DSCP63_PRIORITY_MASK    0x7000
#define    RTL8367D_DSCP62_PRIORITY_OFFSET    8
#define    RTL8367D_DSCP62_PRIORITY_MASK    0x700
#define    RTL8367D_DSCP61_PRIORITY_OFFSET    4
#define    RTL8367D_DSCP61_PRIORITY_MASK    0x70
#define    RTL8367D_DSCP60_PRIORITY_OFFSET    0
#define    RTL8367D_DSCP60_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_PORTBASED_PRIORITY_CTRL0    0x0877
#define    RTL8367D_PORT3_PRIORITY_OFFSET    12
#define    RTL8367D_PORT3_PRIORITY_MASK    0x7000
#define    RTL8367D_PORT2_PRIORITY_OFFSET    8
#define    RTL8367D_PORT2_PRIORITY_MASK    0x700
#define    RTL8367D_PORT1_PRIORITY_OFFSET    4
#define    RTL8367D_PORT1_PRIORITY_MASK    0x70
#define    RTL8367D_PORT0_PRIORITY_OFFSET    0
#define    RTL8367D_PORT0_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_PORTBASED_PRIORITY_CTRL1    0x0878
#define    RTL8367D_PORT7_PRIORITY_OFFSET    12
#define    RTL8367D_PORT7_PRIORITY_MASK    0x7000
#define    RTL8367D_PORT6_PRIORITY_OFFSET    8
#define    RTL8367D_PORT6_PRIORITY_MASK    0x700
#define    RTL8367D_PORT5_PRIORITY_OFFSET    4
#define    RTL8367D_PORT5_PRIORITY_MASK    0x70
#define    RTL8367D_PORT4_PRIORITY_OFFSET    0
#define    RTL8367D_PORT4_PRIORITY_MASK    0x7

#define    RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0    0x087b
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_ACL_WEIGHT_OFFSET    8
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_ACL_WEIGHT_MASK    0x1F00
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_OFFSET    0
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK    0x1F

#define    RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL1    0x087c
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DOT1Q_WEIGHT_OFFSET    8
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DOT1Q_WEIGHT_MASK    0x1F00
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DSCP_WEIGHT_OFFSET    0
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DSCP_WEIGHT_MASK    0x1F

#define    RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL2    0x087d
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_OFFSET    0
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_MASK    0x1F

#define    RTL8367D_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0    0x087f
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_OFFSET    12
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_MASK    0x7000
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_OFFSET    8
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_MASK    0x700
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_OFFSET    4
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_MASK    0x70
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_OFFSET    0
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_MASK    0x7

#define    RTL8367D_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1    0x0880
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_OFFSET    12
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_MASK    0x7000
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_OFFSET    8
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_MASK    0x700
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_OFFSET    4
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_MASK    0x70
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_OFFSET    0
#define    RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_MASK    0x7

#define    RTL8367D_REG_QOS_TRAP_PRIORITY0    0x0881
#define    RTL8367D_UNKNOWN_MC_PRIORTY_OFFSET    12
#define    RTL8367D_UNKNOWN_MC_PRIORTY_MASK    0x7000
#define    RTL8367D_SVLAN_PRIOIRTY_OFFSET    8
#define    RTL8367D_SVLAN_PRIOIRTY_MASK    0x700
#define    RTL8367D_DOT1X_PRIORTY_OFFSET    0
#define    RTL8367D_DOT1X_PRIORTY_MASK    0x7

#define    RTL8367D_REG_QOS_TRAP_PRIORITY1    0x0882
#define    RTL8367D_QOS_TRAP_PRIORITY1_OFFSET    0
#define    RTL8367D_QOS_TRAP_PRIORITY1_MASK    0x7

#define    RTL8367D_REG_MAX_LENGTH_CFG    0x0883
#define    RTL8367D_MAX_LENGTH_GIGA_OFFSET    8
#define    RTL8367D_MAX_LENGTH_GIGA_MASK    0xFF00
#define    RTL8367D_MAX_LENGTH_10_100M_OFFSET    0
#define    RTL8367D_MAX_LENGTH_10_100M_MASK    0xFF

#define    RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0    0x0885
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_ACL_WEIGHT_OFFSET    8
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_ACL_WEIGHT_MASK    0x1F00
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_OFFSET    0
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK    0x1F

#define    RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1    0x0886
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DOT1Q_WEIGHT_OFFSET    8
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DOT1Q_WEIGHT_MASK    0x1F00
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DSCP_WEIGHT_OFFSET    0
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DSCP_WEIGHT_MASK    0x1F

#define    RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2    0x0887
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_OFFSET    0
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_MASK    0x1F

#define    RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_IDX    0x0889
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_IDX_OFFSET    0
#define    RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_IDX_MASK    0xFF

#define    RTL8367D_REG_MAX_LEN_RX_TX_CFG0    0x088c
#define    RTL8367D_MAX_LEN_RX_TX_CFG0_OFFSET    0
#define    RTL8367D_MAX_LEN_RX_TX_CFG0_MASK    0x3FFF

#define    RTL8367D_REG_MAX_LEN_RX_TX_CFG1    0x088d
#define    RTL8367D_MAX_LEN_RX_TX_CFG1_OFFSET    0
#define    RTL8367D_MAX_LEN_RX_TX_CFG1_MASK    0x3FFF

#define    RTL8367D_REG_UNDA_FLOODING_PMSK    0x0890
#define    RTL8367D_UNDA_FLOODING_PMSK_OFFSET    0
#define    RTL8367D_UNDA_FLOODING_PMSK_MASK    0xFF

#define    RTL8367D_REG_UNMCAST_FLOADING_PMSK    0x0891
#define    RTL8367D_UNMCAST_FLOADING_PMSK_OFFSET    0
#define    RTL8367D_UNMCAST_FLOADING_PMSK_MASK    0xFF

#define    RTL8367D_REG_BCAST_FLOADING_PMSK    0x0892
#define    RTL8367D_BCAST_FLOADING_PMSK_OFFSET    0
#define    RTL8367D_BCAST_FLOADING_PMSK_MASK    0xFF

#define    RTL8367D_REG_PORT_ISOLATION_PORT0_MASK    0x08a2
#define    RTL8367D_PORT_ISOLATION_PORT0_MASK_OFFSET    0
#define    RTL8367D_PORT_ISOLATION_PORT0_MASK_MASK    0xFF

#define    RTL8367D_REG_PORT_ISOLATION_PORT1_MASK    0x08a3
#define    RTL8367D_PORT_ISOLATION_PORT1_MASK_OFFSET    0
#define    RTL8367D_PORT_ISOLATION_PORT1_MASK_MASK    0xFF

#define    RTL8367D_REG_PORT_ISOLATION_PORT2_MASK    0x08a4
#define    RTL8367D_PORT_ISOLATION_PORT2_MASK_OFFSET    0
#define    RTL8367D_PORT_ISOLATION_PORT2_MASK_MASK    0xFF

#define    RTL8367D_REG_PORT_ISOLATION_PORT3_MASK    0x08a5
#define    RTL8367D_PORT_ISOLATION_PORT3_MASK_OFFSET    0
#define    RTL8367D_PORT_ISOLATION_PORT3_MASK_MASK    0xFF

#define    RTL8367D_REG_PORT_ISOLATION_PORT4_MASK    0x08a6
#define    RTL8367D_PORT_ISOLATION_PORT4_MASK_OFFSET    0
#define    RTL8367D_PORT_ISOLATION_PORT4_MASK_MASK    0xFF

#define    RTL8367D_REG_PORT_ISOLATION_PORT5_MASK    0x08a7
#define    RTL8367D_PORT_ISOLATION_PORT5_MASK_OFFSET    0
#define    RTL8367D_PORT_ISOLATION_PORT5_MASK_MASK    0xFF

#define    RTL8367D_REG_PORT_ISOLATION_PORT6_MASK    0x08a8
#define    RTL8367D_PORT_ISOLATION_PORT6_MASK_OFFSET    0
#define    RTL8367D_PORT_ISOLATION_PORT6_MASK_MASK    0xFF

#define    RTL8367D_REG_PORT_ISOLATION_PORT7_MASK    0x08a9
#define    RTL8367D_PORT_ISOLATION_PORT7_MASK_OFFSET    0
#define    RTL8367D_PORT_ISOLATION_PORT7_MASK_MASK    0xFF

#define    RTL8367D_REG_FORCE_CTRL    0x08b4
#define    RTL8367D_FORCE_CTRL_OFFSET    0
#define    RTL8367D_FORCE_CTRL_MASK    0xFF

#define    RTL8367D_REG_FORCE_PORT0_MASK    0x08b5
#define    RTL8367D_FORCE_PORT0_MASK_OFFSET    0
#define    RTL8367D_FORCE_PORT0_MASK_MASK    0xFF

#define    RTL8367D_REG_FORCE_PORT1_MASK    0x08b6
#define    RTL8367D_FORCE_PORT1_MASK_OFFSET    0
#define    RTL8367D_FORCE_PORT1_MASK_MASK    0xFF

#define    RTL8367D_REG_FORCE_PORT2_MASK    0x08b7
#define    RTL8367D_FORCE_PORT2_MASK_OFFSET    0
#define    RTL8367D_FORCE_PORT2_MASK_MASK    0xFF

#define    RTL8367D_REG_FORCE_PORT3_MASK    0x08b8
#define    RTL8367D_FORCE_PORT3_MASK_OFFSET    0
#define    RTL8367D_FORCE_PORT3_MASK_MASK    0xFF

#define    RTL8367D_REG_FORCE_PORT4_MASK    0x08b9
#define    RTL8367D_FORCE_PORT4_MASK_OFFSET    0
#define    RTL8367D_FORCE_PORT4_MASK_MASK    0xFF

#define    RTL8367D_REG_FORCE_PORT5_MASK    0x08ba
#define    RTL8367D_FORCE_PORT5_MASK_OFFSET    0
#define    RTL8367D_FORCE_PORT5_MASK_MASK    0xFF

#define    RTL8367D_REG_FORCE_PORT6_MASK    0x08bb
#define    RTL8367D_FORCE_PORT6_MASK_OFFSET    0
#define    RTL8367D_FORCE_PORT6_MASK_MASK    0xFF

#define    RTL8367D_REG_FORCE_PORT7_MASK    0x08bc
#define    RTL8367D_FORCE_PORT7_MASK_OFFSET    0
#define    RTL8367D_FORCE_PORT7_MASK_MASK    0xFF

#define    RTL8367D_REG_LUT_UNKN_SA_CTRL    0x08c0
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT7_ACT_OFFSET    14
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT7_ACT_MASK    0xC000
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT6_ACT_OFFSET    12
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT6_ACT_MASK    0x3000
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT5_ACT_OFFSET    10
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT5_ACT_MASK    0xC00
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT4_ACT_OFFSET    8
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT4_ACT_MASK    0x300
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT3_ACT_OFFSET    6
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT3_ACT_MASK    0xC0
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT2_ACT_OFFSET    4
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT2_ACT_MASK    0x30
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT1_ACT_OFFSET    2
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT1_ACT_MASK    0xC
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT0_ACT_OFFSET    0
#define    RTL8367D_LUT_UNKN_SA_CTRL_PORT0_ACT_MASK    0x3

#define    RTL8367D_REG_LUT_UNMATCHED_SA_CTRL    0x08c1
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT7_ACT_OFFSET    14
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT7_ACT_MASK    0xC000
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT6_ACT_OFFSET    12
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT6_ACT_MASK    0x3000
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT5_ACT_OFFSET    10
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT5_ACT_MASK    0xC00
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT4_ACT_OFFSET    8
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT4_ACT_MASK    0x300
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT3_ACT_OFFSET    6
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT3_ACT_MASK    0xC0
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT2_ACT_OFFSET    4
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT2_ACT_MASK    0x30
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT1_ACT_OFFSET    2
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT1_ACT_MASK    0xC
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT0_ACT_OFFSET    0
#define    RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT0_ACT_MASK    0x3

#define    RTL8367D_REG_SOURCE_PORT_PERMIT    0x08c5
#define    RTL8367D_SOURCE_PORT_PERMIT_OFFSET    0
#define    RTL8367D_SOURCE_PORT_PERMIT_MASK    0xFF

#define    RTL8367D_REG_IPMCAST_VLAN_LEAKY    0x08c6
#define    RTL8367D_IPMCAST_VLAN_LEAKY_OFFSET    0
#define    RTL8367D_IPMCAST_VLAN_LEAKY_MASK    0xFF

#define    RTL8367D_REG_IPMCAST_PORTISO_LEAKY    0x08c7
#define    RTL8367D_IPMCAST_PORTISO_LEAKY_OFFSET    0
#define    RTL8367D_IPMCAST_PORTISO_LEAKY_MASK    0xFF

#define    RTL8367D_REG_PORT_SECURITY_CTRL    0x08c8
#define    RTL8367D_PORT_SECURITY_CTRL_OFFSET    4
#define    RTL8367D_PORT_SECURITY_CTRL_MASK    0x30

#define    RTL8367D_REG_UNKNOWN_IPV4_MULTICAST_CTRL0    0x08c9
#define    RTL8367D_PORT7_UNKNOWN_IP4_MCAST_OFFSET    14
#define    RTL8367D_PORT7_UNKNOWN_IP4_MCAST_MASK    0xC000
#define    RTL8367D_PORT6_UNKNOWN_IP4_MCAST_OFFSET    12
#define    RTL8367D_PORT6_UNKNOWN_IP4_MCAST_MASK    0x3000
#define    RTL8367D_PORT5_UNKNOWN_IP4_MCAST_OFFSET    10
#define    RTL8367D_PORT5_UNKNOWN_IP4_MCAST_MASK    0xC00
#define    RTL8367D_PORT4_UNKNOWN_IP4_MCAST_OFFSET    8
#define    RTL8367D_PORT4_UNKNOWN_IP4_MCAST_MASK    0x300
#define    RTL8367D_PORT3_UNKNOWN_IP4_MCAST_OFFSET    6
#define    RTL8367D_PORT3_UNKNOWN_IP4_MCAST_MASK    0xC0
#define    RTL8367D_PORT2_UNKNOWN_IP4_MCAST_OFFSET    4
#define    RTL8367D_PORT2_UNKNOWN_IP4_MCAST_MASK    0x30
#define    RTL8367D_PORT1_UNKNOWN_IP4_MCAST_OFFSET    2
#define    RTL8367D_PORT1_UNKNOWN_IP4_MCAST_MASK    0xC
#define    RTL8367D_PORT0_UNKNOWN_IP4_MCAST_OFFSET    0
#define    RTL8367D_PORT0_UNKNOWN_IP4_MCAST_MASK    0x3

#define    RTL8367D_REG_UNKNOWN_IPV6_MULTICAST_CTRL0    0x08cb
#define    RTL8367D_PORT7_UNKNOWN_IP6_MCAST_OFFSET    14
#define    RTL8367D_PORT7_UNKNOWN_IP6_MCAST_MASK    0xC000
#define    RTL8367D_PORT6_UNKNOWN_IP6_MCAST_OFFSET    12
#define    RTL8367D_PORT6_UNKNOWN_IP6_MCAST_MASK    0x3000
#define    RTL8367D_PORT5_UNKNOWN_IP6_MCAST_OFFSET    10
#define    RTL8367D_PORT5_UNKNOWN_IP6_MCAST_MASK    0xC00
#define    RTL8367D_PORT4_UNKNOWN_IP6_MCAST_OFFSET    8
#define    RTL8367D_PORT4_UNKNOWN_IP6_MCAST_MASK    0x300
#define    RTL8367D_PORT3_UNKNOWN_IP6_MCAST_OFFSET    6
#define    RTL8367D_PORT3_UNKNOWN_IP6_MCAST_MASK    0xC0
#define    RTL8367D_PORT2_UNKNOWN_IP6_MCAST_OFFSET    4
#define    RTL8367D_PORT2_UNKNOWN_IP6_MCAST_MASK    0x30
#define    RTL8367D_PORT1_UNKNOWN_IP6_MCAST_OFFSET    2
#define    RTL8367D_PORT1_UNKNOWN_IP6_MCAST_MASK    0xC
#define    RTL8367D_PORT0_UNKNOWN_IP6_MCAST_OFFSET    0
#define    RTL8367D_PORT0_UNKNOWN_IP6_MCAST_MASK    0x3

#define    RTL8367D_REG_UNKNOWN_L2_MULTICAST_CTRL0    0x08cd
#define    RTL8367D_PORT7_UNKNOWN_L2_MCAST_OFFSET    14
#define    RTL8367D_PORT7_UNKNOWN_L2_MCAST_MASK    0xC000
#define    RTL8367D_PORT6_UNKNOWN_L2_MCAST_OFFSET    12
#define    RTL8367D_PORT6_UNKNOWN_L2_MCAST_MASK    0x3000
#define    RTL8367D_PORT5_UNKNOWN_L2_MCAST_OFFSET    10
#define    RTL8367D_PORT5_UNKNOWN_L2_MCAST_MASK    0xC00
#define    RTL8367D_PORT4_UNKNOWN_L2_MCAST_OFFSET    8
#define    RTL8367D_PORT4_UNKNOWN_L2_MCAST_MASK    0x300
#define    RTL8367D_PORT3_UNKNOWN_L2_MCAST_OFFSET    6
#define    RTL8367D_PORT3_UNKNOWN_L2_MCAST_MASK    0xC0
#define    RTL8367D_PORT2_UNKNOWN_L2_MCAST_OFFSET    4
#define    RTL8367D_PORT2_UNKNOWN_L2_MCAST_MASK    0x30
#define    RTL8367D_PORT1_UNKNOWN_L2_MCAST_OFFSET    2
#define    RTL8367D_PORT1_UNKNOWN_L2_MCAST_MASK    0xC
#define    RTL8367D_PORT0_UNKNOWN_L2_MCAST_OFFSET    0
#define    RTL8367D_PORT0_UNKNOWN_L2_MCAST_MASK    0x3

#define    RTL8367D_REG_PORT_TRUNK_DROP_CTRL    0x08ce
#define    RTL8367D_PORT_TRUNK_DROP_CTRL_OFFSET    0
#define    RTL8367D_PORT_TRUNK_DROP_CTRL_MASK    0x1

#define    RTL8367D_REG_PORT_TRUNK_CTRL    0x08cf
#define    RTL8367D_GROUP1_DPORT_HASH_OFFSET    15
#define    RTL8367D_GROUP1_DPORT_HASH_MASK    0x8000
#define    RTL8367D_GROUP1_SPORT_HASH_OFFSET    14
#define    RTL8367D_GROUP1_SPORT_HASH_MASK    0x4000
#define    RTL8367D_GROUP1_DIP_HASH_OFFSET    13
#define    RTL8367D_GROUP1_DIP_HASH_MASK    0x2000
#define    RTL8367D_GROUP1_SIP_HASH_OFFSET    12
#define    RTL8367D_GROUP1_SIP_HASH_MASK    0x1000
#define    RTL8367D_GROUP1_DMAC_HASH_OFFSET    11
#define    RTL8367D_GROUP1_DMAC_HASH_MASK    0x800
#define    RTL8367D_GROUP1_SMAC_HASH_OFFSET    10
#define    RTL8367D_GROUP1_SMAC_HASH_MASK    0x400
#define    RTL8367D_GROUP1_SPA_HASH_OFFSET    9
#define    RTL8367D_GROUP1_SPA_HASH_MASK    0x200
#define    RTL8367D_PORT_TRUNK_DUMB_OFFSET    8
#define    RTL8367D_PORT_TRUNK_DUMB_MASK    0x100
#define    RTL8367D_PORT_TRUNK_FLOOD_OFFSET    7
#define    RTL8367D_PORT_TRUNK_FLOOD_MASK    0x80
#define    RTL8367D_GROUP0_DPORT_HASH_OFFSET    6
#define    RTL8367D_GROUP0_DPORT_HASH_MASK    0x40
#define    RTL8367D_GROUP0_SPORT_HASH_OFFSET    5
#define    RTL8367D_GROUP0_SPORT_HASH_MASK    0x20
#define    RTL8367D_GROUP0_DIP_HASH_OFFSET    4
#define    RTL8367D_GROUP0_DIP_HASH_MASK    0x10
#define    RTL8367D_GROUP0_SIP_HASH_OFFSET    3
#define    RTL8367D_GROUP0_SIP_HASH_MASK    0x8
#define    RTL8367D_GROUP0_DMAC_HASH_OFFSET    2
#define    RTL8367D_GROUP0_DMAC_HASH_MASK    0x4
#define    RTL8367D_GROUP0_SMAC_HASH_OFFSET    1
#define    RTL8367D_GROUP0_SMAC_HASH_MASK    0x2
#define    RTL8367D_GROUP0_SPA_HASH_OFFSET    0
#define    RTL8367D_GROUP0_SPA_HASH_MASK    0x1

#define    RTL8367D_REG_PORT_TRUNK_GROUP_MASK    0x08d0
#define    RTL8367D_PORT_TRUNK_GROUP1_MASK_OFFSET    4
#define    RTL8367D_PORT_TRUNK_GROUP1_MASK_MASK    0xF0
#define    RTL8367D_PORT_TRUNK_GROUP0_MASK_OFFSET    0
#define    RTL8367D_PORT_TRUNK_GROUP0_MASK_MASK    0xF

#define    RTL8367D_REG_PORT_TRUNK_FLOWCTRL    0x08d1
#define    RTL8367D_EN_FLOWCTRL_TG1_OFFSET    1
#define    RTL8367D_EN_FLOWCTRL_TG1_MASK    0x2
#define    RTL8367D_EN_FLOWCTRL_TG0_OFFSET    0
#define    RTL8367D_EN_FLOWCTRL_TG0_MASK    0x1

#define    RTL8367D_REG_PORT_TRUNK_HASH_MAPPING_CTRL0    0x08d2
#define    RTL8367D_HASH7_OFFSET    14
#define    RTL8367D_HASH7_MASK    0xC000
#define    RTL8367D_HASH6_OFFSET    12
#define    RTL8367D_HASH6_MASK    0x3000
#define    RTL8367D_HASH5_OFFSET    10
#define    RTL8367D_HASH5_MASK    0xC00
#define    RTL8367D_HASH4_OFFSET    8
#define    RTL8367D_HASH4_MASK    0x300
#define    RTL8367D_HASH3_OFFSET    6
#define    RTL8367D_HASH3_MASK    0xC0
#define    RTL8367D_HASH2_OFFSET    4
#define    RTL8367D_HASH2_MASK    0x30
#define    RTL8367D_HASH1_OFFSET    2
#define    RTL8367D_HASH1_MASK    0xC
#define    RTL8367D_HASH0_OFFSET    0
#define    RTL8367D_HASH0_MASK    0x3

#define    RTL8367D_REG_PORT_TRUNK_HASH_MAPPING_CTRL1    0x08d3
#define    RTL8367D_HASH15_OFFSET    14
#define    RTL8367D_HASH15_MASK    0xC000
#define    RTL8367D_HASH14_OFFSET    12
#define    RTL8367D_HASH14_MASK    0x3000
#define    RTL8367D_HASH13_OFFSET    10
#define    RTL8367D_HASH13_MASK    0xC00
#define    RTL8367D_HASH12_OFFSET    8
#define    RTL8367D_HASH12_MASK    0x300
#define    RTL8367D_HASH11_OFFSET    6
#define    RTL8367D_HASH11_MASK    0xC0
#define    RTL8367D_HASH10_OFFSET    4
#define    RTL8367D_HASH10_MASK    0x30
#define    RTL8367D_HASH9_OFFSET    2
#define    RTL8367D_HASH9_MASK    0xC
#define    RTL8367D_HASH8_OFFSET    0
#define    RTL8367D_HASH8_MASK    0x3

#define    RTL8367D_REG_DOS_CFG    0x08d4
#define    RTL8367D_DROP_ICMPFRAGMENT_OFFSET    9
#define    RTL8367D_DROP_ICMPFRAGMENT_MASK    0x200
#define    RTL8367D_DROP_TCPFRAGERROR_OFFSET    8
#define    RTL8367D_DROP_TCPFRAGERROR_MASK    0x100
#define    RTL8367D_DROP_TCPSHORTHDR_OFFSET    7
#define    RTL8367D_DROP_TCPSHORTHDR_MASK    0x80
#define    RTL8367D_DROP_SYN1024_OFFSET    6
#define    RTL8367D_DROP_SYN1024_MASK    0x40
#define    RTL8367D_DROP_NULLSCAN_OFFSET    5
#define    RTL8367D_DROP_NULLSCAN_MASK    0x20
#define    RTL8367D_DROP_XMASCAN_OFFSET    4
#define    RTL8367D_DROP_XMASCAN_MASK    0x10
#define    RTL8367D_DROP_SYNFINSCAN_OFFSET    3
#define    RTL8367D_DROP_SYNFINSCAN_MASK    0x8
#define    RTL8367D_DROP_BLATATTACKS_OFFSET    2
#define    RTL8367D_DROP_BLATATTACKS_MASK    0x4
#define    RTL8367D_DROP_LANDATTACKS_OFFSET    1
#define    RTL8367D_DROP_LANDATTACKS_MASK    0x2
#define    RTL8367D_DROP_DAEQSA_OFFSET    0
#define    RTL8367D_DROP_DAEQSA_MASK    0x1

#define    RTL8367D_REG_FPGA_VER_CEN    0x08e0

#define    RTL8367D_REG_FPGA_TIME_CEN    0x08e1

#define    RTL8367D_REG_FPGA_DATE_CEN    0x08e2

#define    RTL8367D_REG_QOS_PORT_QUEUE_NUMBER_CTRL0    0x0900
#define    RTL8367D_PORT3_NUMBER_OFFSET    12
#define    RTL8367D_PORT3_NUMBER_MASK    0x7000
#define    RTL8367D_PORT2_NUMBER_OFFSET    8
#define    RTL8367D_PORT2_NUMBER_MASK    0x700
#define    RTL8367D_PORT1_NUMBER_OFFSET    4
#define    RTL8367D_PORT1_NUMBER_MASK    0x70
#define    RTL8367D_PORT0_NUMBER_OFFSET    0
#define    RTL8367D_PORT0_NUMBER_MASK    0x7

#define    RTL8367D_REG_QOS_PORT_QUEUE_NUMBER_CTRL1    0x0901
#define    RTL8367D_PORT7_NUMBER_OFFSET    12
#define    RTL8367D_PORT7_NUMBER_MASK    0x7000
#define    RTL8367D_PORT6_NUMBER_OFFSET    8
#define    RTL8367D_PORT6_NUMBER_MASK    0x700
#define    RTL8367D_PORT5_NUMBER_OFFSET    4
#define    RTL8367D_PORT5_NUMBER_MASK    0x70
#define    RTL8367D_PORT4_NUMBER_OFFSET    0
#define    RTL8367D_PORT4_NUMBER_MASK    0x7

#define    RTL8367D_REG_QOS_1Q_PRIORITY_TO_QID_CTRL0    0x0904
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_1Q_PRIORITY_TO_QID_CTRL1    0x0905
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_2Q_PRIORITY_TO_QID_CTRL0    0x0906
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_2Q_PRIORITY_TO_QID_CTRL1    0x0907
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_3Q_PRIORITY_TO_QID_CTRL0    0x0908
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_3Q_PRIORITY_TO_QID_CTRL1    0x0909
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_4Q_PRIORITY_TO_QID_CTRL0    0x090a
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_4Q_PRIORITY_TO_QID_CTRL1    0x090b
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_5Q_PRIORITY_TO_QID_CTRL0    0x090c
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_5Q_PRIORITY_TO_QID_CTRL1    0x090d
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_6Q_PRIORITY_TO_QID_CTRL0    0x090e
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_6Q_PRIORITY_TO_QID_CTRL1    0x090f
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_7Q_PRIORITY_TO_QID_CTRL0    0x0910
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_7Q_PRIORITY_TO_QID_CTRL1    0x0911
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_8Q_PRIORITY_TO_QID_CTRL0    0x0912
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7

#define    RTL8367D_REG_QOS_8Q_PRIORITY_TO_QID_CTRL1    0x0913
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0
#define    RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7

#define    RTL8367D_REG_PORT_DEBUG_INFO_CTRL0    0x0917
#define    RTL8367D_PORT1_DEBUG_INFO_OFFSET    8
#define    RTL8367D_PORT1_DEBUG_INFO_MASK    0xFF00
#define    RTL8367D_PORT0_DEBUG_INFO_OFFSET    0
#define    RTL8367D_PORT0_DEBUG_INFO_MASK    0xFF

#define    RTL8367D_REG_PORT_DEBUG_INFO_CTRL1    0x0918
#define    RTL8367D_PORT3_DEBUG_INFO_OFFSET    8
#define    RTL8367D_PORT3_DEBUG_INFO_MASK    0xFF00
#define    RTL8367D_PORT2_DEBUG_INFO_OFFSET    0
#define    RTL8367D_PORT2_DEBUG_INFO_MASK    0xFF

#define    RTL8367D_REG_PORT_DEBUG_INFO_CTRL2    0x0919
#define    RTL8367D_PORT5_DEBUG_INFO_OFFSET    8
#define    RTL8367D_PORT5_DEBUG_INFO_MASK    0xFF00
#define    RTL8367D_PORT4_DEBUG_INFO_OFFSET    0
#define    RTL8367D_PORT4_DEBUG_INFO_MASK    0xFF

#define    RTL8367D_REG_PORT_DEBUG_INFO_CTRL3    0x091a
#define    RTL8367D_PORT7_DEBUG_INFO_OFFSET    8
#define    RTL8367D_PORT7_DEBUG_INFO_MASK    0xFF00
#define    RTL8367D_PORT6_DEBUG_INFO_OFFSET    0
#define    RTL8367D_PORT6_DEBUG_INFO_MASK    0xFF

#define    RTL8367D_REG_PORT_DEBUG_INFO_CTRL4    0x091d
#define    RTL8367D_PORT7_DEBUG_INDICATOR_OFFSET    14
#define    RTL8367D_PORT7_DEBUG_INDICATOR_MASK    0xC000
#define    RTL8367D_PORT6_DEBUG_INDICATOR_OFFSET    12
#define    RTL8367D_PORT6_DEBUG_INDICATOR_MASK    0x3000
#define    RTL8367D_PORT5_DEBUG_INDICATOR_OFFSET    10
#define    RTL8367D_PORT5_DEBUG_INDICATOR_MASK    0xC00
#define    RTL8367D_PORT4_DEBUG_INDICATOR_OFFSET    8
#define    RTL8367D_PORT4_DEBUG_INDICATOR_MASK    0x300
#define    RTL8367D_PORT3_DEBUG_INDICATOR_OFFSET    6
#define    RTL8367D_PORT3_DEBUG_INDICATOR_MASK    0xC0
#define    RTL8367D_PORT2_DEBUG_INDICATOR_OFFSET    4
#define    RTL8367D_PORT2_DEBUG_INDICATOR_MASK    0x30
#define    RTL8367D_PORT1_DEBUG_INDICATOR_OFFSET    2
#define    RTL8367D_PORT1_DEBUG_INDICATOR_MASK    0xC
#define    RTL8367D_PORT0_DEBUG_INDICATOR_OFFSET    0
#define    RTL8367D_PORT0_DEBUG_INDICATOR_MASK    0x3

#define    RTL8367D_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL0    0x0930
#define    RTL8367D_PORT1_QUEUE_MASK_OFFSET    8
#define    RTL8367D_PORT1_QUEUE_MASK_MASK    0xFF00
#define    RTL8367D_PORT0_QUEUE_MASK_OFFSET    0
#define    RTL8367D_PORT0_QUEUE_MASK_MASK    0xFF

#define    RTL8367D_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL1    0x0931
#define    RTL8367D_PORT3_QUEUE_MASK_OFFSET    8
#define    RTL8367D_PORT3_QUEUE_MASK_MASK    0xFF00
#define    RTL8367D_PORT2_QUEUE_MASK_OFFSET    0
#define    RTL8367D_PORT2_QUEUE_MASK_MASK    0xFF

#define    RTL8367D_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL2    0x0932
#define    RTL8367D_PORT5_QUEUE_MASK_OFFSET    8
#define    RTL8367D_PORT5_QUEUE_MASK_MASK    0xFF00
#define    RTL8367D_PORT4_QUEUE_MASK_OFFSET    0
#define    RTL8367D_PORT4_QUEUE_MASK_MASK    0xFF

#define    RTL8367D_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL3    0x0933
#define    RTL8367D_PORT7_QUEUE_MASK_OFFSET    8
#define    RTL8367D_PORT7_QUEUE_MASK_MASK    0xFF00
#define    RTL8367D_PORT6_QUEUE_MASK_OFFSET    0
#define    RTL8367D_PORT6_QUEUE_MASK_MASK    0xFF

#define    RTL8367D_REG_VLAN_EGRESS_KEEP_CTRL0    0x093b
#define    RTL8367D_PORT1_VLAN_KEEP_MASK_OFFSET    8
#define    RTL8367D_PORT1_VLAN_KEEP_MASK_MASK    0xFF00
#define    RTL8367D_PORT0_VLAN_KEEP_MASK_OFFSET    0
#define    RTL8367D_PORT0_VLAN_KEEP_MASK_MASK    0xFF

#define    RTL8367D_REG_VLAN_EGRESS_KEEP_CTRL1    0x093c
#define    RTL8367D_PORT3_VLAN_KEEP_MASK_OFFSET    8
#define    RTL8367D_PORT3_VLAN_KEEP_MASK_MASK    0xFF00
#define    RTL8367D_PORT2_VLAN_KEEP_MASK_OFFSET    0
#define    RTL8367D_PORT2_VLAN_KEEP_MASK_MASK    0xFF

#define    RTL8367D_REG_VLAN_EGRESS_KEEP_CTRL2    0x093d
#define    RTL8367D_PORT5_VLAN_KEEP_MASK_OFFSET    8
#define    RTL8367D_PORT5_VLAN_KEEP_MASK_MASK    0xFF00
#define    RTL8367D_PORT4_VLAN_KEEP_MASK_OFFSET    0
#define    RTL8367D_PORT4_VLAN_KEEP_MASK_MASK    0xFF

#define    RTL8367D_REG_VLAN_EGRESS_KEEP_CTRL3    0x093e
#define    RTL8367D_PORT7_VLAN_KEEP_MASK_OFFSET    8
#define    RTL8367D_PORT7_VLAN_KEEP_MASK_MASK    0xFF00
#define    RTL8367D_PORT6_VLAN_KEEP_MASK_OFFSET    0
#define    RTL8367D_PORT6_VLAN_KEEP_MASK_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY0_H    0x0940
#define    RTL8367D_IPMC_GROUP_ENTRY0_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY0_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY0_L    0x0941

#define    RTL8367D_REG_IPMC_GROUP_ENTRY1_H    0x0942
#define    RTL8367D_IPMC_GROUP_ENTRY1_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY1_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY1_L    0x0943

#define    RTL8367D_REG_IPMC_GROUP_ENTRY2_H    0x0944
#define    RTL8367D_IPMC_GROUP_ENTRY2_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY2_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY2_L    0x0945

#define    RTL8367D_REG_IPMC_GROUP_ENTRY3_H    0x0946
#define    RTL8367D_IPMC_GROUP_ENTRY3_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY3_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY3_L    0x0947

#define    RTL8367D_REG_IPMC_GROUP_ENTRY4_H    0x0948
#define    RTL8367D_IPMC_GROUP_ENTRY4_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY4_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY4_L    0x0949

#define    RTL8367D_REG_IPMC_GROUP_ENTRY5_H    0x094a
#define    RTL8367D_IPMC_GROUP_ENTRY5_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY5_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY5_L    0x094b

#define    RTL8367D_REG_IPMC_GROUP_ENTRY6_H    0x094c
#define    RTL8367D_IPMC_GROUP_ENTRY6_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY6_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY6_L    0x094d

#define    RTL8367D_REG_IPMC_GROUP_ENTRY7_H    0x094e
#define    RTL8367D_IPMC_GROUP_ENTRY7_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY7_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY7_L    0x094f

#define    RTL8367D_REG_IPMC_GROUP_ENTRY8_H    0x0950
#define    RTL8367D_IPMC_GROUP_ENTRY8_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY8_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY8_L    0x0951

#define    RTL8367D_REG_IPMC_GROUP_ENTRY9_H    0x0952
#define    RTL8367D_IPMC_GROUP_ENTRY9_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY9_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY9_L    0x0953

#define    RTL8367D_REG_IPMC_GROUP_ENTRY10_H    0x0954
#define    RTL8367D_IPMC_GROUP_ENTRY10_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY10_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY10_L    0x0955

#define    RTL8367D_REG_IPMC_GROUP_ENTRY11_H    0x0956
#define    RTL8367D_IPMC_GROUP_ENTRY11_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY11_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY11_L    0x0957

#define    RTL8367D_REG_IPMC_GROUP_ENTRY12_H    0x0958
#define    RTL8367D_IPMC_GROUP_ENTRY12_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY12_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY12_L    0x0959

#define    RTL8367D_REG_IPMC_GROUP_ENTRY13_H    0x095a
#define    RTL8367D_IPMC_GROUP_ENTRY13_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY13_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY13_L    0x095b

#define    RTL8367D_REG_IPMC_GROUP_ENTRY14_H    0x095c
#define    RTL8367D_IPMC_GROUP_ENTRY14_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY14_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY14_L    0x095d

#define    RTL8367D_REG_IPMC_GROUP_ENTRY15_H    0x095e
#define    RTL8367D_IPMC_GROUP_ENTRY15_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY15_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY15_L    0x095f

#define    RTL8367D_REG_IPMC_GROUP_ENTRY16_H    0x0960
#define    RTL8367D_IPMC_GROUP_ENTRY16_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY16_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY16_L    0x0961

#define    RTL8367D_REG_IPMC_GROUP_ENTRY17_H    0x0962
#define    RTL8367D_IPMC_GROUP_ENTRY17_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY17_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY17_L    0x0963

#define    RTL8367D_REG_IPMC_GROUP_ENTRY18_H    0x0964
#define    RTL8367D_IPMC_GROUP_ENTRY18_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY18_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY18_L    0x0965

#define    RTL8367D_REG_IPMC_GROUP_ENTRY19_H    0x0966
#define    RTL8367D_IPMC_GROUP_ENTRY19_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY19_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY19_L    0x0967

#define    RTL8367D_REG_IPMC_GROUP_ENTRY20_H    0x0968
#define    RTL8367D_IPMC_GROUP_ENTRY20_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY20_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY20_L    0x0969

#define    RTL8367D_REG_IPMC_GROUP_ENTRY21_H    0x096a
#define    RTL8367D_IPMC_GROUP_ENTRY21_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY21_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY21_L    0x096b

#define    RTL8367D_REG_IPMC_GROUP_ENTRY22_H    0x096c
#define    RTL8367D_IPMC_GROUP_ENTRY22_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY22_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY22_L    0x096d

#define    RTL8367D_REG_IPMC_GROUP_ENTRY23_H    0x096e
#define    RTL8367D_IPMC_GROUP_ENTRY23_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY23_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY23_L    0x096f

#define    RTL8367D_REG_IPMC_GROUP_ENTRY24_H    0x0970
#define    RTL8367D_IPMC_GROUP_ENTRY24_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY24_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY24_L    0x0971

#define    RTL8367D_REG_IPMC_GROUP_ENTRY25_H    0x0972
#define    RTL8367D_IPMC_GROUP_ENTRY25_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY25_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY25_L    0x0973

#define    RTL8367D_REG_IPMC_GROUP_ENTRY26_H    0x0974
#define    RTL8367D_IPMC_GROUP_ENTRY26_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY26_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY26_L    0x0975

#define    RTL8367D_REG_IPMC_GROUP_ENTRY27_H    0x0976
#define    RTL8367D_IPMC_GROUP_ENTRY27_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY27_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY27_L    0x0977

#define    RTL8367D_REG_IPMC_GROUP_ENTRY28_H    0x0978
#define    RTL8367D_IPMC_GROUP_ENTRY28_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY28_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY28_L    0x0979

#define    RTL8367D_REG_IPMC_GROUP_ENTRY29_H    0x097a
#define    RTL8367D_IPMC_GROUP_ENTRY29_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY29_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY29_L    0x097b

#define    RTL8367D_REG_IPMC_GROUP_ENTRY30_H    0x097c
#define    RTL8367D_IPMC_GROUP_ENTRY30_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY30_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY30_L    0x097d

#define    RTL8367D_REG_IPMC_GROUP_ENTRY31_H    0x097e
#define    RTL8367D_IPMC_GROUP_ENTRY31_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY31_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY31_L    0x097f

#define    RTL8367D_REG_IPMC_GROUP_ENTRY32_H    0x0980
#define    RTL8367D_IPMC_GROUP_ENTRY32_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY32_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY32_L    0x0981

#define    RTL8367D_REG_IPMC_GROUP_ENTRY33_H    0x0982
#define    RTL8367D_IPMC_GROUP_ENTRY33_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY33_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY33_L    0x0983

#define    RTL8367D_REG_IPMC_GROUP_ENTRY34_H    0x0984
#define    RTL8367D_IPMC_GROUP_ENTRY34_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY34_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY34_L    0x0985

#define    RTL8367D_REG_IPMC_GROUP_ENTRY35_H    0x0986
#define    RTL8367D_IPMC_GROUP_ENTRY35_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY35_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY35_L    0x0987

#define    RTL8367D_REG_IPMC_GROUP_ENTRY36_H    0x0988
#define    RTL8367D_IPMC_GROUP_ENTRY36_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY36_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY36_L    0x0989

#define    RTL8367D_REG_IPMC_GROUP_ENTRY37_H    0x098a
#define    RTL8367D_IPMC_GROUP_ENTRY37_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY37_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY37_L    0x098b

#define    RTL8367D_REG_IPMC_GROUP_ENTRY38_H    0x098c
#define    RTL8367D_IPMC_GROUP_ENTRY38_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY38_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY38_L    0x098d

#define    RTL8367D_REG_IPMC_GROUP_ENTRY39_H    0x098e
#define    RTL8367D_IPMC_GROUP_ENTRY39_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY39_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY39_L    0x098f

#define    RTL8367D_REG_IPMC_GROUP_ENTRY40_H    0x0990
#define    RTL8367D_IPMC_GROUP_ENTRY40_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY40_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY40_L    0x0991

#define    RTL8367D_REG_IPMC_GROUP_ENTRY41_H    0x0992
#define    RTL8367D_IPMC_GROUP_ENTRY41_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY41_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY41_L    0x0993

#define    RTL8367D_REG_IPMC_GROUP_ENTRY42_H    0x0994
#define    RTL8367D_IPMC_GROUP_ENTRY42_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY42_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY42_L    0x0995

#define    RTL8367D_REG_IPMC_GROUP_ENTRY43_H    0x0996
#define    RTL8367D_IPMC_GROUP_ENTRY43_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY43_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY43_L    0x0997

#define    RTL8367D_REG_IPMC_GROUP_ENTRY44_H    0x0998
#define    RTL8367D_IPMC_GROUP_ENTRY44_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY44_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY44_L    0x0999

#define    RTL8367D_REG_IPMC_GROUP_ENTRY45_H    0x099a
#define    RTL8367D_IPMC_GROUP_ENTRY45_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY45_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY45_L    0x099b

#define    RTL8367D_REG_IPMC_GROUP_ENTRY46_H    0x099c
#define    RTL8367D_IPMC_GROUP_ENTRY46_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY46_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY46_L    0x099d

#define    RTL8367D_REG_IPMC_GROUP_ENTRY47_H    0x099e
#define    RTL8367D_IPMC_GROUP_ENTRY47_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY47_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY47_L    0x099f

#define    RTL8367D_REG_IPMC_GROUP_ENTRY48_H    0x09a0
#define    RTL8367D_IPMC_GROUP_ENTRY48_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY48_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY48_L    0x09a1

#define    RTL8367D_REG_IPMC_GROUP_ENTRY49_H    0x09a2
#define    RTL8367D_IPMC_GROUP_ENTRY49_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY49_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY49_L    0x09a3

#define    RTL8367D_REG_IPMC_GROUP_ENTRY50_H    0x09a4
#define    RTL8367D_IPMC_GROUP_ENTRY50_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY50_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY50_L    0x09a5

#define    RTL8367D_REG_IPMC_GROUP_ENTRY51_H    0x09a6
#define    RTL8367D_IPMC_GROUP_ENTRY51_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY51_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY51_L    0x09a7

#define    RTL8367D_REG_IPMC_GROUP_ENTRY52_H    0x09a8
#define    RTL8367D_IPMC_GROUP_ENTRY52_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY52_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY52_L    0x09a9

#define    RTL8367D_REG_IPMC_GROUP_ENTRY53_H    0x09aa
#define    RTL8367D_IPMC_GROUP_ENTRY53_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY53_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY53_L    0x09ab

#define    RTL8367D_REG_IPMC_GROUP_ENTRY54_H    0x09ac
#define    RTL8367D_IPMC_GROUP_ENTRY54_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY54_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY54_L    0x09ad

#define    RTL8367D_REG_IPMC_GROUP_ENTRY55_H    0x09ae
#define    RTL8367D_IPMC_GROUP_ENTRY55_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY55_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY55_L    0x09af

#define    RTL8367D_REG_IPMC_GROUP_ENTRY56_H    0x09b0
#define    RTL8367D_IPMC_GROUP_ENTRY56_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY56_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY56_L    0x09b1

#define    RTL8367D_REG_IPMC_GROUP_ENTRY57_H    0x09b2
#define    RTL8367D_IPMC_GROUP_ENTRY57_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY57_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY57_L    0x09b3

#define    RTL8367D_REG_IPMC_GROUP_ENTRY58_H    0x09b4
#define    RTL8367D_IPMC_GROUP_ENTRY58_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY58_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY58_L    0x09b5

#define    RTL8367D_REG_IPMC_GROUP_ENTRY59_H    0x09b6
#define    RTL8367D_IPMC_GROUP_ENTRY59_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY59_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY59_L    0x09b7

#define    RTL8367D_REG_IPMC_GROUP_ENTRY60_H    0x09b8
#define    RTL8367D_IPMC_GROUP_ENTRY60_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY60_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY60_L    0x09b9

#define    RTL8367D_REG_IPMC_GROUP_ENTRY61_H    0x09ba
#define    RTL8367D_IPMC_GROUP_ENTRY61_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY61_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY61_L    0x09bb

#define    RTL8367D_REG_IPMC_GROUP_ENTRY62_H    0x09bc
#define    RTL8367D_IPMC_GROUP_ENTRY62_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY62_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY62_L    0x09bd

#define    RTL8367D_REG_IPMC_GROUP_ENTRY63_H    0x09be
#define    RTL8367D_IPMC_GROUP_ENTRY63_H_OFFSET    0
#define    RTL8367D_IPMC_GROUP_ENTRY63_H_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_ENTRY63_L    0x09bf

#define    RTL8367D_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE    0x09C0
#define    RTL8367D_Port7_ACTION_OFFSET    14
#define    RTL8367D_Port7_ACTION_MASK    0xC000
#define    RTL8367D_Port6_ACTION_OFFSET    12
#define    RTL8367D_Port6_ACTION_MASK    0x3000
#define    RTL8367D_Port5_ACTION_OFFSET    10
#define    RTL8367D_Port5_ACTION_MASK    0xC00
#define    RTL8367D_Port4_ACTION_OFFSET    8
#define    RTL8367D_Port4_ACTION_MASK    0x300
#define    RTL8367D_Port3_ACTION_OFFSET    6
#define    RTL8367D_Port3_ACTION_MASK    0xC0
#define    RTL8367D_Port2_ACTION_OFFSET    4
#define    RTL8367D_Port2_ACTION_MASK    0x30
#define    RTL8367D_Port1_ACTION_OFFSET    2
#define    RTL8367D_Port1_ACTION_MASK    0xC
#define    RTL8367D_Port0_ACTION_OFFSET    0
#define    RTL8367D_Port0_ACTION_MASK    0x3

#define    RTL8367D_REG_MIRROR_OVERRIDE_CFG    0x09C1
#define    RTL8367D_MIRROR_ACL_OVERRIDE_EN_OFFSET    2
#define    RTL8367D_MIRROR_ACL_OVERRIDE_EN_MASK    0x4
#define    RTL8367D_MIRROR_TX_OVERRIDE_EN_OFFSET    1
#define    RTL8367D_MIRROR_TX_OVERRIDE_EN_MASK    0x2
#define    RTL8367D_MIRROR_RX_OVERRIDE_EN_OFFSET    0
#define    RTL8367D_MIRROR_RX_OVERRIDE_EN_MASK    0x1

#define    RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL0    0x09D0
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL0_OFFSET    0
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL0_MASK    0xFF

#define    RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL1    0x09D1
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL1_OFFSET    0
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL1_MASK    0xFF

#define    RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL2    0x09D2
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL2_OFFSET    0
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL2_MASK    0xFF

#define    RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL3    0x09D3
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL3_OFFSET    0
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL3_MASK    0xFF

#define    RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL4    0x09D4
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL4_OFFSET    0
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL4_MASK    0xFF

#define    RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL5    0x09D5
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL5_OFFSET    0
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL5_MASK    0xFF

#define    RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL6    0x09D6
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL6_OFFSET    0
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL6_MASK    0xFF

#define    RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL7    0x09D7
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL7_OFFSET    0
#define    RTL8367D_VLAN_EGRESS_TRANS_CTRL7_MASK    0xFF

#define    RTL8367D_REG_MIRROR_CTRL2    0x09DA
#define    RTL8367D_MIRROR_REALKEEP_EN_OFFSET    4
#define    RTL8367D_MIRROR_REALKEEP_EN_MASK    0x10
#define    RTL8367D_MIRROR_RX_ISOLATION_LEAKY_OFFSET    3
#define    RTL8367D_MIRROR_RX_ISOLATION_LEAKY_MASK    0x8
#define    RTL8367D_MIRROR_TX_ISOLATION_LEAKY_OFFSET    2
#define    RTL8367D_MIRROR_TX_ISOLATION_LEAKY_MASK    0x4
#define    RTL8367D_MIRROR_RX_VLAN_LEAKY_OFFSET    1
#define    RTL8367D_MIRROR_RX_VLAN_LEAKY_MASK    0x2
#define    RTL8367D_MIRROR_TX_VLAN_LEAKY_OFFSET    0
#define    RTL8367D_MIRROR_TX_VLAN_LEAKY_MASK    0x1

#define    RTL8367D_REG_OUTPUT_DROP_CFG    0x09DB
#define    RTL8367D_ENABLE_BC_OFFSET    12
#define    RTL8367D_ENABLE_BC_MASK    0x1000
#define    RTL8367D_ENABLE_MC_OFFSET    11
#define    RTL8367D_ENABLE_MC_MASK    0x800
#define    RTL8367D_ENABLE_UC_OFFSET    10
#define    RTL8367D_ENABLE_UC_MASK    0x400
#define    RTL8367D_ENABLE_PMASK_OFFSET    0
#define    RTL8367D_ENABLE_PMASK_MASK    0xFF

#define    RTL8367D_REG_RMK_CFG_SEL_CTRL    0x09DF
#define    RTL8367D_RMK_1Q_CFG_SEL_OFFSET    2
#define    RTL8367D_RMK_1Q_CFG_SEL_MASK    0x4
#define    RTL8367D_RMK_DSCP_CFG_SEL_OFFSET    0
#define    RTL8367D_RMK_DSCP_CFG_SEL_MASK    0x1

/* (16'h0a00)l2_reg */

#define    RTL8367D_REG_VLAN_MSTI0_CTRL0    0x0a00
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8367D_VLAN_MSTI0_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8367D_REG_VLAN_MSTI1_CTRL0    0x0a02
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8367D_VLAN_MSTI1_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8367D_REG_VLAN_MSTI2_CTRL0    0x0a04
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8367D_VLAN_MSTI2_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8367D_REG_VLAN_MSTI3_CTRL0    0x0a06
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT7_STATE_OFFSET    14
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT7_STATE_MASK    0xC000
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT6_STATE_OFFSET    12
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT6_STATE_MASK    0x3000
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT5_STATE_OFFSET    10
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT5_STATE_MASK    0xC00
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT4_STATE_OFFSET    8
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT4_STATE_MASK    0x300
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT3_STATE_OFFSET    6
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT3_STATE_MASK    0xC0
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT2_STATE_OFFSET    4
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT2_STATE_MASK    0x30
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT1_STATE_OFFSET    2
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT1_STATE_MASK    0xC
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT0_STATE_OFFSET    0
#define    RTL8367D_VLAN_MSTI3_CTRL0_PORT0_STATE_MASK    0x3

#define    RTL8367D_REG_LOOKUP_HIT_ISO_ACT    0x0a10
#define    RTL8367D_LOOKUP_HIT_ISO_ACT_OFFSET    0
#define    RTL8367D_LOOKUP_HIT_ISO_ACT_MASK    0x1

#define    RTL8367D_REG_LUT_PORT0_LEARN_LIMITNO    0x0a20
#define    RTL8367D_LUT_PORT0_LEARN_LIMITNO_OFFSET    0
#define    RTL8367D_LUT_PORT0_LEARN_LIMITNO_MASK    0xFFF

#define    RTL8367D_REG_LUT_PORT1_LEARN_LIMITNO    0x0a21
#define    RTL8367D_LUT_PORT1_LEARN_LIMITNO_OFFSET    0
#define    RTL8367D_LUT_PORT1_LEARN_LIMITNO_MASK    0xFFF

#define    RTL8367D_REG_LUT_PORT2_LEARN_LIMITNO    0x0a22
#define    RTL8367D_LUT_PORT2_LEARN_LIMITNO_OFFSET    0
#define    RTL8367D_LUT_PORT2_LEARN_LIMITNO_MASK    0xFFF

#define    RTL8367D_REG_LUT_PORT3_LEARN_LIMITNO    0x0a23
#define    RTL8367D_LUT_PORT3_LEARN_LIMITNO_OFFSET    0
#define    RTL8367D_LUT_PORT3_LEARN_LIMITNO_MASK    0xFFF

#define    RTL8367D_REG_LUT_PORT4_LEARN_LIMITNO    0x0a24
#define    RTL8367D_LUT_PORT4_LEARN_LIMITNO_OFFSET    0
#define    RTL8367D_LUT_PORT4_LEARN_LIMITNO_MASK    0xFFF

#define    RTL8367D_REG_LUT_PORT5_LEARN_LIMITNO    0x0a25
#define    RTL8367D_LUT_PORT5_LEARN_LIMITNO_OFFSET    0
#define    RTL8367D_LUT_PORT5_LEARN_LIMITNO_MASK    0xFFF

#define    RTL8367D_REG_LUT_PORT6_LEARN_LIMITNO    0x0a26
#define    RTL8367D_LUT_PORT6_LEARN_LIMITNO_OFFSET    0
#define    RTL8367D_LUT_PORT6_LEARN_LIMITNO_MASK    0xFFF

#define    RTL8367D_REG_LUT_PORT7_LEARN_LIMITNO    0x0a27
#define    RTL8367D_LUT_PORT7_LEARN_LIMITNO_OFFSET    0
#define    RTL8367D_LUT_PORT7_LEARN_LIMITNO_MASK    0xFFF

#define    RTL8367D_REG_LUT_SYS_LEARN_LIMITNO    0x0a28
#define    RTL8367D_LUT_SYS_LEARN_LIMITNO_OFFSET    0
#define    RTL8367D_LUT_SYS_LEARN_LIMITNO_MASK    0xFFF

#define    RTL8367D_REG_LUT_LRN_SYS_LMT_CTRL    0x0a29
#define    RTL8367D_LUT_SYSTEM_LEARN_OVER_ACT_OFFSET    10
#define    RTL8367D_LUT_SYSTEM_LEARN_OVER_ACT_MASK    0xC00
#define    RTL8367D_LUT_SYSTEM_LEARN_PMASK_OFFSET    0
#define    RTL8367D_LUT_SYSTEM_LEARN_PMASK_MASK    0xFF

#define    RTL8367D_REG_LUT_CFG    0x0a30
#define    RTL8367D_BCAM_DISABLE_OFFSET    6
#define    RTL8367D_BCAM_DISABLE_MASK    0x40
#define    RTL8367D_LINKDOWN_AGEOUT_OFFSET    5
#define    RTL8367D_LINKDOWN_AGEOUT_MASK    0x20
#define    RTL8367D_LUT_IPMC_HASH_OFFSET    4
#define    RTL8367D_LUT_IPMC_HASH_MASK    0x10
#define    RTL8367D_LUT_CFG_AGE_TIMER_OFFSET    0
#define    RTL8367D_LUT_CFG_AGE_TIMER_MASK    0x7

#define    RTL8367D_REG_LUT_AGEOUT_CTRL    0x0a31
#define    RTL8367D_LUT_AGEOUT_CTRL_OFFSET    0
#define    RTL8367D_LUT_AGEOUT_CTRL_MASK    0xFF

#define    RTL8367D_REG_LUT_CFG2    0x0a32

#define    RTL8367D_REG_FORCE_FLUSH    0x0a36
#define    RTL8367D_BUSY_STATUS_OFFSET    8
#define    RTL8367D_BUSY_STATUS_MASK    0xFF00
#define    RTL8367D_FORCE_FLUSH_PORTMASK_OFFSET    0
#define    RTL8367D_FORCE_FLUSH_PORTMASK_MASK    0xFF

#define    RTL8367D_REG_L2_FLUSH_CTRL1    0x0a37
#define    RTL8367D_LUT_FLUSH_FID_OFFSET    12
#define    RTL8367D_LUT_FLUSH_FID_MASK    0x3000
#define    RTL8367D_LUT_FLUSH_VID_OFFSET    0
#define    RTL8367D_LUT_FLUSH_VID_MASK    0xFFF

#define    RTL8367D_REG_L2_FLUSH_CTRL2    0x0a38
#define    RTL8367D_LUT_FLUSH_TYPE_OFFSET    2
#define    RTL8367D_LUT_FLUSH_TYPE_MASK    0x4
#define    RTL8367D_LUT_FLUSH_MODE_OFFSET    0
#define    RTL8367D_LUT_FLUSH_MODE_MASK    0x3

#define    RTL8367D_REG_L2_FLUSH_CTRL3    0x0a39
#define    RTL8367D_L2_FLUSH_CTRL3_OFFSET    0
#define    RTL8367D_L2_FLUSH_CTRL3_MASK    0x1

#define    RTL8367D_REG_FLUSH_STATUS    0x0a3f
#define    RTL8367D_FLUSH_STATUS_OFFSET    0
#define    RTL8367D_FLUSH_STATUS_MASK    0x1

#define    RTL8367D_REG_STORM_BCAST    0x0a40
#define    RTL8367D_STORM_BCAST_OFFSET    0
#define    RTL8367D_STORM_BCAST_MASK    0xFF

#define    RTL8367D_REG_STORM_MCAST    0x0a41
#define    RTL8367D_STORM_MCAST_OFFSET    0
#define    RTL8367D_STORM_MCAST_MASK    0xFF

#define    RTL8367D_REG_STORM_UNKOWN_UCAST    0x0a42
#define    RTL8367D_STORM_UNKOWN_UCAST_OFFSET    0
#define    RTL8367D_STORM_UNKOWN_UCAST_MASK    0xFF

#define    RTL8367D_REG_STORM_UNKOWN_MCAST    0x0a43
#define    RTL8367D_STORM_UNKOWN_MCAST_OFFSET    0
#define    RTL8367D_STORM_UNKOWN_MCAST_MASK    0xFF

#define    RTL8367D_REG_STORM_BCAST_METER_CTRL0    0x0a44
#define    RTL8367D_STORM_BCAST_METER_CTRL0_PORT1_METERIDX_OFFSET    8
#define    RTL8367D_STORM_BCAST_METER_CTRL0_PORT1_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_BCAST_METER_CTRL0_PORT0_METERIDX_OFFSET    0
#define    RTL8367D_STORM_BCAST_METER_CTRL0_PORT0_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_BCAST_METER_CTRL1    0x0a45
#define    RTL8367D_STORM_BCAST_METER_CTRL1_PORT3_METERIDX_OFFSET    8
#define    RTL8367D_STORM_BCAST_METER_CTRL1_PORT3_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_BCAST_METER_CTRL1_PORT2_METERIDX_OFFSET    0
#define    RTL8367D_STORM_BCAST_METER_CTRL1_PORT2_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_BCAST_METER_CTRL2    0x0a46
#define    RTL8367D_STORM_BCAST_METER_CTRL2_PORT5_METERIDX_OFFSET    8
#define    RTL8367D_STORM_BCAST_METER_CTRL2_PORT5_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_BCAST_METER_CTRL2_PORT4_METERIDX_OFFSET    0
#define    RTL8367D_STORM_BCAST_METER_CTRL2_PORT4_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_BCAST_METER_CTRL3    0x0a47
#define    RTL8367D_STORM_BCAST_METER_CTRL3_PORT7_METERIDX_OFFSET    8
#define    RTL8367D_STORM_BCAST_METER_CTRL3_PORT7_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_BCAST_METER_CTRL3_PORT6_METERIDX_OFFSET    0
#define    RTL8367D_STORM_BCAST_METER_CTRL3_PORT6_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_MCAST_METER_CTRL0    0x0a4c
#define    RTL8367D_STORM_MCAST_METER_CTRL0_PORT1_METERIDX_OFFSET    8
#define    RTL8367D_STORM_MCAST_METER_CTRL0_PORT1_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_MCAST_METER_CTRL0_PORT0_METERIDX_OFFSET    0
#define    RTL8367D_STORM_MCAST_METER_CTRL0_PORT0_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_MCAST_METER_CTRL1    0x0a4d
#define    RTL8367D_STORM_MCAST_METER_CTRL1_PORT3_METERIDX_OFFSET    8
#define    RTL8367D_STORM_MCAST_METER_CTRL1_PORT3_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_MCAST_METER_CTRL1_PORT2_METERIDX_OFFSET    0
#define    RTL8367D_STORM_MCAST_METER_CTRL1_PORT2_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_MCAST_METER_CTRL2    0x0a4e
#define    RTL8367D_STORM_MCAST_METER_CTRL2_PORT5_METERIDX_OFFSET    8
#define    RTL8367D_STORM_MCAST_METER_CTRL2_PORT5_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_MCAST_METER_CTRL2_PORT4_METERIDX_OFFSET    0
#define    RTL8367D_STORM_MCAST_METER_CTRL2_PORT4_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_MCAST_METER_CTRL3    0x0a4f
#define    RTL8367D_STORM_MCAST_METER_CTRL3_PORT7_METERIDX_OFFSET    8
#define    RTL8367D_STORM_MCAST_METER_CTRL3_PORT7_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_MCAST_METER_CTRL3_PORT6_METERIDX_OFFSET    0
#define    RTL8367D_STORM_MCAST_METER_CTRL3_PORT6_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_UNDA_METER_CTRL0    0x0a54
#define    RTL8367D_STORM_UNDA_METER_CTRL0_PORT1_METERIDX_OFFSET    8
#define    RTL8367D_STORM_UNDA_METER_CTRL0_PORT1_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_UNDA_METER_CTRL0_PORT0_METERIDX_OFFSET    0
#define    RTL8367D_STORM_UNDA_METER_CTRL0_PORT0_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_UNDA_METER_CTRL1    0x0a55
#define    RTL8367D_STORM_UNDA_METER_CTRL1_PORT3_METERIDX_OFFSET    8
#define    RTL8367D_STORM_UNDA_METER_CTRL1_PORT3_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_UNDA_METER_CTRL1_PORT2_METERIDX_OFFSET    0
#define    RTL8367D_STORM_UNDA_METER_CTRL1_PORT2_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_UNDA_METER_CTRL2    0x0a56
#define    RTL8367D_STORM_UNDA_METER_CTRL2_PORT5_METERIDX_OFFSET    8
#define    RTL8367D_STORM_UNDA_METER_CTRL2_PORT5_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_UNDA_METER_CTRL2_PORT4_METERIDX_OFFSET    0
#define    RTL8367D_STORM_UNDA_METER_CTRL2_PORT4_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_UNDA_METER_CTRL3    0x0a57
#define    RTL8367D_STORM_UNDA_METER_CTRL3_PORT7_METERIDX_OFFSET    8
#define    RTL8367D_STORM_UNDA_METER_CTRL3_PORT7_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_UNDA_METER_CTRL3_PORT6_METERIDX_OFFSET    0
#define    RTL8367D_STORM_UNDA_METER_CTRL3_PORT6_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_UNMC_METER_CTRL0    0x0a5c
#define    RTL8367D_STORM_UNMC_METER_CTRL0_PORT1_METERIDX_OFFSET    8
#define    RTL8367D_STORM_UNMC_METER_CTRL0_PORT1_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_UNMC_METER_CTRL0_PORT0_METERIDX_OFFSET    0
#define    RTL8367D_STORM_UNMC_METER_CTRL0_PORT0_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_UNMC_METER_CTRL1    0x0a5d
#define    RTL8367D_STORM_UNMC_METER_CTRL1_PORT3_METERIDX_OFFSET    8
#define    RTL8367D_STORM_UNMC_METER_CTRL1_PORT3_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_UNMC_METER_CTRL1_PORT2_METERIDX_OFFSET    0
#define    RTL8367D_STORM_UNMC_METER_CTRL1_PORT2_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_UNMC_METER_CTRL2    0x0a5e
#define    RTL8367D_STORM_UNMC_METER_CTRL2_PORT5_METERIDX_OFFSET    8
#define    RTL8367D_STORM_UNMC_METER_CTRL2_PORT5_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_UNMC_METER_CTRL2_PORT4_METERIDX_OFFSET    0
#define    RTL8367D_STORM_UNMC_METER_CTRL2_PORT4_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_UNMC_METER_CTRL3    0x0a5f
#define    RTL8367D_STORM_UNMC_METER_CTRL3_PORT7_METERIDX_OFFSET    8
#define    RTL8367D_STORM_UNMC_METER_CTRL3_PORT7_METERIDX_MASK    0x3F00
#define    RTL8367D_STORM_UNMC_METER_CTRL3_PORT6_METERIDX_OFFSET    0
#define    RTL8367D_STORM_UNMC_METER_CTRL3_PORT6_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_EXT_CFG    0x0a60
#define    RTL8367D_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET    13
#define    RTL8367D_STORM_UNKNOWN_MCAST_EXT_EN_MASK    0x2000
#define    RTL8367D_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET    12
#define    RTL8367D_STORM_UNKNOWN_UCAST_EXT_EN_MASK    0x1000
#define    RTL8367D_STORM_MCAST_EXT_EN_OFFSET    11
#define    RTL8367D_STORM_MCAST_EXT_EN_MASK    0x800
#define    RTL8367D_STORM_BCAST_EXT_EN_OFFSET    10
#define    RTL8367D_STORM_BCAST_EXT_EN_MASK    0x400
#define    RTL8367D_STORM_EXT_EN_PORTMASK_OFFSET    0
#define    RTL8367D_STORM_EXT_EN_PORTMASK_MASK    0xFF

#define    RTL8367D_REG_STORM_EXT_MTRIDX_CFG0    0x0a61
#define    RTL8367D_MC_STORM_EXT_METERIDX_OFFSET    8
#define    RTL8367D_MC_STORM_EXT_METERIDX_MASK    0x3F00
#define    RTL8367D_BC_STORM_EXT_METERIDX_OFFSET    0
#define    RTL8367D_BC_STORM_EXT_METERIDX_MASK    0x3F

#define    RTL8367D_REG_STORM_EXT_MTRIDX_CFG1    0x0a62
#define    RTL8367D_UNMC_STORM_EXT_METERIDX_OFFSET    8
#define    RTL8367D_UNMC_STORM_EXT_METERIDX_MASK    0x3F00
#define    RTL8367D_UNUC_STORM_EXT_METERIDX_OFFSET    0
#define    RTL8367D_UNUC_STORM_EXT_METERIDX_MASK    0x3F

#define    RTL8367D_REG_DOT1X_PORT_ENABLE    0x0a80
#define    RTL8367D_DOT1X_PORT_ENABLE_OFFSET    0
#define    RTL8367D_DOT1X_PORT_ENABLE_MASK    0xFF

#define    RTL8367D_REG_DOT1X_PORT_AUTH    0x0a82
#define    RTL8367D_DOT1X_PORT_AUTH_OFFSET    0
#define    RTL8367D_DOT1X_PORT_AUTH_MASK    0xFF

#define    RTL8367D_REG_DOT1X_PORT_OPDIR    0x0a83
#define    RTL8367D_DOT1X_PORT_OPDIR_OFFSET    0
#define    RTL8367D_DOT1X_PORT_OPDIR_MASK    0xFF

#define    RTL8367D_REG_DOT1X_UNAUTH_ACT_W0    0x0a84
#define    RTL8367D_DOT1X_PORT7_UNAUTHBH_OFFSET    7
#define    RTL8367D_DOT1X_PORT7_UNAUTHBH_MASK    0x80
#define    RTL8367D_DOT1X_PORT6_UNAUTHBH_OFFSET    6
#define    RTL8367D_DOT1X_PORT6_UNAUTHBH_MASK    0x40
#define    RTL8367D_DOT1X_PORT5_UNAUTHBH_OFFSET    5
#define    RTL8367D_DOT1X_PORT5_UNAUTHBH_MASK    0x20
#define    RTL8367D_DOT1X_PORT4_UNAUTHBH_OFFSET    4
#define    RTL8367D_DOT1X_PORT4_UNAUTHBH_MASK    0x10
#define    RTL8367D_DOT1X_PORT3_UNAUTHBH_OFFSET    3
#define    RTL8367D_DOT1X_PORT3_UNAUTHBH_MASK    0x8
#define    RTL8367D_DOT1X_PORT2_UNAUTHBH_OFFSET    2
#define    RTL8367D_DOT1X_PORT2_UNAUTHBH_MASK    0x4
#define    RTL8367D_DOT1X_PORT1_UNAUTHBH_OFFSET    1
#define    RTL8367D_DOT1X_PORT1_UNAUTHBH_MASK    0x2
#define    RTL8367D_DOT1X_PORT0_UNAUTHBH_OFFSET    0
#define    RTL8367D_DOT1X_PORT0_UNAUTHBH_MASK    0x1

#define    RTL8367D_REG_L2_LRN_CNT_CTRL0    0x0a87
#define    RTL8367D_L2_LRN_CNT_CTRL0_OFFSET    0
#define    RTL8367D_L2_LRN_CNT_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_L2_LRN_CNT_CTRL1    0x0a88
#define    RTL8367D_L2_LRN_CNT_CTRL1_OFFSET    0
#define    RTL8367D_L2_LRN_CNT_CTRL1_MASK    0xFFF

#define    RTL8367D_REG_L2_LRN_CNT_CTRL2    0x0a89
#define    RTL8367D_L2_LRN_CNT_CTRL2_OFFSET    0
#define    RTL8367D_L2_LRN_CNT_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_L2_LRN_CNT_CTRL3    0x0a8a
#define    RTL8367D_L2_LRN_CNT_CTRL3_OFFSET    0
#define    RTL8367D_L2_LRN_CNT_CTRL3_MASK    0xFFF

#define    RTL8367D_REG_L2_LRN_CNT_CTRL4    0x0a8b
#define    RTL8367D_L2_LRN_CNT_CTRL4_OFFSET    0
#define    RTL8367D_L2_LRN_CNT_CTRL4_MASK    0xFFF

#define    RTL8367D_REG_L2_LRN_CNT_CTRL5    0x0a8c
#define    RTL8367D_L2_LRN_CNT_CTRL5_OFFSET    0
#define    RTL8367D_L2_LRN_CNT_CTRL5_MASK    0xFFF

#define    RTL8367D_REG_L2_LRN_CNT_CTRL6    0x0a8d
#define    RTL8367D_L2_LRN_CNT_CTRL6_OFFSET    0
#define    RTL8367D_L2_LRN_CNT_CTRL6_MASK    0xFFF

#define    RTL8367D_REG_L2_LRN_CNT_CTRL7    0x0a8e
#define    RTL8367D_L2_LRN_CNT_CTRL7_OFFSET    0
#define    RTL8367D_L2_LRN_CNT_CTRL7_MASK    0xFFF

#define    RTL8367D_REG_LUT_LRN_UNDER_STATUS    0x0a91
#define    RTL8367D_LUT_LRN_UNDER_STATUS_OFFSET    0
#define    RTL8367D_LUT_LRN_UNDER_STATUS_MASK    0xFF

#define    RTL8367D_REG_L2_SA_MOVING_FORBID    0x0aa0
#define    RTL8367D_L2_SA_MOVING_FORBID_OFFSET    0
#define    RTL8367D_L2_SA_MOVING_FORBID_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_00    0x0AC0
#define    RTL8367D_IPMC_GROUP_PMSK_00_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_00_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_01    0x0AC1
#define    RTL8367D_IPMC_GROUP_PMSK_01_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_01_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_02    0x0AC2
#define    RTL8367D_IPMC_GROUP_PMSK_02_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_02_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_03    0x0AC3
#define    RTL8367D_IPMC_GROUP_PMSK_03_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_03_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_04    0x0AC4
#define    RTL8367D_IPMC_GROUP_PMSK_04_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_04_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_05    0x0AC5
#define    RTL8367D_IPMC_GROUP_PMSK_05_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_05_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_06    0x0AC6
#define    RTL8367D_IPMC_GROUP_PMSK_06_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_06_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_07    0x0AC7
#define    RTL8367D_IPMC_GROUP_PMSK_07_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_07_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_08    0x0AC8
#define    RTL8367D_IPMC_GROUP_PMSK_08_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_08_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_09    0x0AC9
#define    RTL8367D_IPMC_GROUP_PMSK_09_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_09_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_10    0x0ACA
#define    RTL8367D_IPMC_GROUP_PMSK_10_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_10_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_11    0x0ACB
#define    RTL8367D_IPMC_GROUP_PMSK_11_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_11_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_12    0x0ACC
#define    RTL8367D_IPMC_GROUP_PMSK_12_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_12_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_13    0x0ACD
#define    RTL8367D_IPMC_GROUP_PMSK_13_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_13_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_14    0x0ACE
#define    RTL8367D_IPMC_GROUP_PMSK_14_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_14_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_15    0x0ACF
#define    RTL8367D_IPMC_GROUP_PMSK_15_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_15_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_16    0x0AD0
#define    RTL8367D_IPMC_GROUP_PMSK_16_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_16_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_17    0x0AD1
#define    RTL8367D_IPMC_GROUP_PMSK_17_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_17_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_18    0x0AD2
#define    RTL8367D_IPMC_GROUP_PMSK_18_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_18_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_19    0x0AD3
#define    RTL8367D_IPMC_GROUP_PMSK_19_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_19_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_20    0x0AD4
#define    RTL8367D_IPMC_GROUP_PMSK_20_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_20_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_21    0x0AD5
#define    RTL8367D_IPMC_GROUP_PMSK_21_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_21_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_22    0x0AD6
#define    RTL8367D_IPMC_GROUP_PMSK_22_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_22_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_23    0x0AD7
#define    RTL8367D_IPMC_GROUP_PMSK_23_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_23_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_24    0x0AD8
#define    RTL8367D_IPMC_GROUP_PMSK_24_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_24_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_25    0x0AD9
#define    RTL8367D_IPMC_GROUP_PMSK_25_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_25_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_26    0x0ADA
#define    RTL8367D_IPMC_GROUP_PMSK_26_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_26_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_27    0x0ADB
#define    RTL8367D_IPMC_GROUP_PMSK_27_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_27_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_28    0x0ADC
#define    RTL8367D_IPMC_GROUP_PMSK_28_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_28_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_29    0x0ADD
#define    RTL8367D_IPMC_GROUP_PMSK_29_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_29_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_30    0x0ADE
#define    RTL8367D_IPMC_GROUP_PMSK_30_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_30_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_31    0x0ADF
#define    RTL8367D_IPMC_GROUP_PMSK_31_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_31_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_32    0x0AE0
#define    RTL8367D_IPMC_GROUP_PMSK_32_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_32_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_33    0x0AE1
#define    RTL8367D_IPMC_GROUP_PMSK_33_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_33_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_34    0x0AE2
#define    RTL8367D_IPMC_GROUP_PMSK_34_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_34_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_35    0x0AE3
#define    RTL8367D_IPMC_GROUP_PMSK_35_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_35_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_36    0x0AE4
#define    RTL8367D_IPMC_GROUP_PMSK_36_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_36_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_37    0x0AE5
#define    RTL8367D_IPMC_GROUP_PMSK_37_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_37_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_38    0x0AE6
#define    RTL8367D_IPMC_GROUP_PMSK_38_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_38_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_39    0x0AE7
#define    RTL8367D_IPMC_GROUP_PMSK_39_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_39_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_40    0x0AE8
#define    RTL8367D_IPMC_GROUP_PMSK_40_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_40_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_41    0x0AE9
#define    RTL8367D_IPMC_GROUP_PMSK_41_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_41_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_42    0x0AEA
#define    RTL8367D_IPMC_GROUP_PMSK_42_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_42_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_43    0x0AEB
#define    RTL8367D_IPMC_GROUP_PMSK_43_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_43_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_44    0x0AEC
#define    RTL8367D_IPMC_GROUP_PMSK_44_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_44_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_45    0x0AED
#define    RTL8367D_IPMC_GROUP_PMSK_45_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_45_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_46    0x0AEE
#define    RTL8367D_IPMC_GROUP_PMSK_46_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_46_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_47    0x0AEF
#define    RTL8367D_IPMC_GROUP_PMSK_47_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_47_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_48    0x0AF0
#define    RTL8367D_IPMC_GROUP_PMSK_48_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_48_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_49    0x0AF1
#define    RTL8367D_IPMC_GROUP_PMSK_49_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_49_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_50    0x0AF2
#define    RTL8367D_IPMC_GROUP_PMSK_50_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_50_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_51    0x0AF3
#define    RTL8367D_IPMC_GROUP_PMSK_51_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_51_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_52    0x0AF4
#define    RTL8367D_IPMC_GROUP_PMSK_52_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_52_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_53    0x0AF5
#define    RTL8367D_IPMC_GROUP_PMSK_53_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_53_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_54    0x0AF6
#define    RTL8367D_IPMC_GROUP_PMSK_54_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_54_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_55    0x0AF7
#define    RTL8367D_IPMC_GROUP_PMSK_55_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_55_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_56    0x0AF8
#define    RTL8367D_IPMC_GROUP_PMSK_56_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_56_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_57    0x0AF9
#define    RTL8367D_IPMC_GROUP_PMSK_57_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_57_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_58    0x0AFA
#define    RTL8367D_IPMC_GROUP_PMSK_58_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_58_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_59    0x0AFB
#define    RTL8367D_IPMC_GROUP_PMSK_59_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_59_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_60    0x0AFC
#define    RTL8367D_IPMC_GROUP_PMSK_60_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_60_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_61    0x0AFD
#define    RTL8367D_IPMC_GROUP_PMSK_61_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_61_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_62    0x0AFE
#define    RTL8367D_IPMC_GROUP_PMSK_62_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_62_MASK    0xFF

#define    RTL8367D_REG_IPMC_GROUP_PMSK_63    0x0AFF
#define    RTL8367D_IPMC_GROUP_PMSK_63_OFFSET    0
#define    RTL8367D_IPMC_GROUP_PMSK_63_MASK    0xFF

/* (16'h0c00)svlan_reg */

#define    RTL8367D_REG_SVLAN_C2SCFG0_CTRL0    0x0d00
#define    RTL8367D_SVLAN_C2SCFG0_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG0_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG0_CTRL1    0x0d01
#define    RTL8367D_SVLAN_C2SCFG0_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG0_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG0_CTRL2    0x0d02
#define    RTL8367D_SVLAN_C2SCFG0_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG0_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG1_CTRL0    0x0d03
#define    RTL8367D_SVLAN_C2SCFG1_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG1_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG1_CTRL1    0x0d04
#define    RTL8367D_SVLAN_C2SCFG1_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG1_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG1_CTRL2    0x0d05
#define    RTL8367D_SVLAN_C2SCFG1_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG1_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG2_CTRL0    0x0d06
#define    RTL8367D_SVLAN_C2SCFG2_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG2_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG2_CTRL1    0x0d07
#define    RTL8367D_SVLAN_C2SCFG2_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG2_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG2_CTRL2    0x0d08
#define    RTL8367D_SVLAN_C2SCFG2_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG2_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG3_CTRL0    0x0d09
#define    RTL8367D_SVLAN_C2SCFG3_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG3_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG3_CTRL1    0x0d0a
#define    RTL8367D_SVLAN_C2SCFG3_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG3_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG3_CTRL2    0x0d0b
#define    RTL8367D_SVLAN_C2SCFG3_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG3_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG4_CTRL0    0x0d0c
#define    RTL8367D_SVLAN_C2SCFG4_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG4_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG4_CTRL1    0x0d0d
#define    RTL8367D_SVLAN_C2SCFG4_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG4_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG4_CTRL2    0x0d0e
#define    RTL8367D_SVLAN_C2SCFG4_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG4_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG5_CTRL0    0x0d0f
#define    RTL8367D_SVLAN_C2SCFG5_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG5_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG5_CTRL1    0x0d10
#define    RTL8367D_SVLAN_C2SCFG5_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG5_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG5_CTRL2    0x0d11
#define    RTL8367D_SVLAN_C2SCFG5_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG5_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG6_CTRL0    0x0d12
#define    RTL8367D_SVLAN_C2SCFG6_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG6_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG6_CTRL1    0x0d13
#define    RTL8367D_SVLAN_C2SCFG6_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG6_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG6_CTRL2    0x0d14
#define    RTL8367D_SVLAN_C2SCFG6_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG6_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG7_CTRL0    0x0d15
#define    RTL8367D_SVLAN_C2SCFG7_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG7_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG7_CTRL1    0x0d16
#define    RTL8367D_SVLAN_C2SCFG7_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG7_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG7_CTRL2    0x0d17
#define    RTL8367D_SVLAN_C2SCFG7_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG7_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG8_CTRL0    0x0d18
#define    RTL8367D_SVLAN_C2SCFG8_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG8_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG8_CTRL1    0x0d19
#define    RTL8367D_SVLAN_C2SCFG8_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG8_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG8_CTRL2    0x0d1a
#define    RTL8367D_SVLAN_C2SCFG8_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG8_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG9_CTRL0    0x0d1b
#define    RTL8367D_SVLAN_C2SCFG9_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG9_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG9_CTRL1    0x0d1c
#define    RTL8367D_SVLAN_C2SCFG9_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG9_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG9_CTRL2    0x0d1d
#define    RTL8367D_SVLAN_C2SCFG9_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG9_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG10_CTRL0    0x0d1e
#define    RTL8367D_SVLAN_C2SCFG10_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG10_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG10_CTRL1    0x0d1f
#define    RTL8367D_SVLAN_C2SCFG10_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG10_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG10_CTRL2    0x0d20
#define    RTL8367D_SVLAN_C2SCFG10_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG10_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG11_CTRL0    0x0d21
#define    RTL8367D_SVLAN_C2SCFG11_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG11_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG11_CTRL1    0x0d22
#define    RTL8367D_SVLAN_C2SCFG11_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG11_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG11_CTRL2    0x0d23
#define    RTL8367D_SVLAN_C2SCFG11_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG11_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG12_CTRL0    0x0d24
#define    RTL8367D_SVLAN_C2SCFG12_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG12_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG12_CTRL1    0x0d25
#define    RTL8367D_SVLAN_C2SCFG12_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG12_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG12_CTRL2    0x0d26
#define    RTL8367D_SVLAN_C2SCFG12_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG12_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG13_CTRL0    0x0d27
#define    RTL8367D_SVLAN_C2SCFG13_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG13_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG13_CTRL1    0x0d28
#define    RTL8367D_SVLAN_C2SCFG13_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG13_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG13_CTRL2    0x0d29
#define    RTL8367D_SVLAN_C2SCFG13_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG13_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG14_CTRL0    0x0d2a
#define    RTL8367D_SVLAN_C2SCFG14_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG14_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG14_CTRL1    0x0d2b
#define    RTL8367D_SVLAN_C2SCFG14_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG14_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG14_CTRL2    0x0d2c
#define    RTL8367D_SVLAN_C2SCFG14_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG14_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG15_CTRL0    0x0d2d
#define    RTL8367D_SVLAN_C2SCFG15_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG15_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG15_CTRL1    0x0d2e
#define    RTL8367D_SVLAN_C2SCFG15_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG15_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG15_CTRL2    0x0d2f
#define    RTL8367D_SVLAN_C2SCFG15_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG15_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG16_CTRL0    0x0d30
#define    RTL8367D_SVLAN_C2SCFG16_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG16_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG16_CTRL1    0x0d31
#define    RTL8367D_SVLAN_C2SCFG16_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG16_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG16_CTRL2    0x0d32
#define    RTL8367D_SVLAN_C2SCFG16_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG16_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG17_CTRL0    0x0d33
#define    RTL8367D_SVLAN_C2SCFG17_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG17_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG17_CTRL1    0x0d34
#define    RTL8367D_SVLAN_C2SCFG17_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG17_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG17_CTRL2    0x0d35
#define    RTL8367D_SVLAN_C2SCFG17_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG17_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG18_CTRL0    0x0d36
#define    RTL8367D_SVLAN_C2SCFG18_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG18_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG18_CTRL1    0x0d37
#define    RTL8367D_SVLAN_C2SCFG18_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG18_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG18_CTRL2    0x0d38
#define    RTL8367D_SVLAN_C2SCFG18_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG18_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG19_CTRL0    0x0d39
#define    RTL8367D_SVLAN_C2SCFG19_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG19_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG19_CTRL1    0x0d3a
#define    RTL8367D_SVLAN_C2SCFG19_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG19_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG19_CTRL2    0x0d3b
#define    RTL8367D_SVLAN_C2SCFG19_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG19_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG20_CTRL0    0x0d3c
#define    RTL8367D_SVLAN_C2SCFG20_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG20_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG20_CTRL1    0x0d3d
#define    RTL8367D_SVLAN_C2SCFG20_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG20_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG20_CTRL2    0x0d3e
#define    RTL8367D_SVLAN_C2SCFG20_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG20_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG21_CTRL0    0x0d3f
#define    RTL8367D_SVLAN_C2SCFG21_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG21_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG21_CTRL1    0x0d40
#define    RTL8367D_SVLAN_C2SCFG21_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG21_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG21_CTRL2    0x0d41
#define    RTL8367D_SVLAN_C2SCFG21_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG21_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG22_CTRL0    0x0d42
#define    RTL8367D_SVLAN_C2SCFG22_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG22_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG22_CTRL1    0x0d43
#define    RTL8367D_SVLAN_C2SCFG22_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG22_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG22_CTRL2    0x0d44
#define    RTL8367D_SVLAN_C2SCFG22_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG22_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG23_CTRL0    0x0d45
#define    RTL8367D_SVLAN_C2SCFG23_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG23_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG23_CTRL1    0x0d46
#define    RTL8367D_SVLAN_C2SCFG23_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG23_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG23_CTRL2    0x0d47
#define    RTL8367D_SVLAN_C2SCFG23_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG23_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG24_CTRL0    0x0d48
#define    RTL8367D_SVLAN_C2SCFG24_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG24_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG24_CTRL1    0x0d49
#define    RTL8367D_SVLAN_C2SCFG24_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG24_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG24_CTRL2    0x0d4a
#define    RTL8367D_SVLAN_C2SCFG24_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG24_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG25_CTRL0    0x0d4b
#define    RTL8367D_SVLAN_C2SCFG25_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG25_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG25_CTRL1    0x0d4c
#define    RTL8367D_SVLAN_C2SCFG25_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG25_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG25_CTRL2    0x0d4d
#define    RTL8367D_SVLAN_C2SCFG25_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG25_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG26_CTRL0    0x0d4e
#define    RTL8367D_SVLAN_C2SCFG26_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG26_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG26_CTRL1    0x0d4f
#define    RTL8367D_SVLAN_C2SCFG26_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG26_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG26_CTRL2    0x0d50
#define    RTL8367D_SVLAN_C2SCFG26_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG26_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG27_CTRL0    0x0d51
#define    RTL8367D_SVLAN_C2SCFG27_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG27_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG27_CTRL1    0x0d52
#define    RTL8367D_SVLAN_C2SCFG27_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG27_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG27_CTRL2    0x0d53
#define    RTL8367D_SVLAN_C2SCFG27_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG27_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG28_CTRL0    0x0d54
#define    RTL8367D_SVLAN_C2SCFG28_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG28_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG28_CTRL1    0x0d55
#define    RTL8367D_SVLAN_C2SCFG28_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG28_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG28_CTRL2    0x0d56
#define    RTL8367D_SVLAN_C2SCFG28_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG28_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG29_CTRL0    0x0d57
#define    RTL8367D_SVLAN_C2SCFG29_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG29_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG29_CTRL1    0x0d58
#define    RTL8367D_SVLAN_C2SCFG29_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG29_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG29_CTRL2    0x0d59
#define    RTL8367D_SVLAN_C2SCFG29_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG29_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG30_CTRL0    0x0d5a
#define    RTL8367D_SVLAN_C2SCFG30_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG30_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG30_CTRL1    0x0d5b
#define    RTL8367D_SVLAN_C2SCFG30_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG30_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG30_CTRL2    0x0d5c
#define    RTL8367D_SVLAN_C2SCFG30_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG30_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG31_CTRL0    0x0d5d
#define    RTL8367D_SVLAN_C2SCFG31_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG31_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_C2SCFG31_CTRL1    0x0d5e
#define    RTL8367D_SVLAN_C2SCFG31_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG31_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SVLAN_C2SCFG31_CTRL2    0x0d5f
#define    RTL8367D_SVLAN_C2SCFG31_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_C2SCFG31_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_CFG    0x0e80
#define    RTL8367D_VS_UIFSEG_OFFSET    6
#define    RTL8367D_VS_UIFSEG_MASK    0x40
#define    RTL8367D_VS_UNTAG_OFFSET    2
#define    RTL8367D_VS_UNTAG_MASK    0xC
#define    RTL8367D_VS_SPRISEL_OFFSET    0
#define    RTL8367D_VS_SPRISEL_MASK    0x3

#define    RTL8367D_REG_SVLAN_UNTAG_UNMAT_CFG    0x0e85
#define    RTL8367D_SVLAN_UNTAG_UNMAT_CFG_OFFSET    0
#define    RTL8367D_SVLAN_UNTAG_UNMAT_CFG_MASK    0xFFF

#define    RTL8367D_REG_IPMC_GROUP_VALID_15_0    0x0e87

#define    RTL8367D_REG_IPMC_GROUP_VALID_31_16    0x0e88

#define    RTL8367D_REG_IPMC_GROUP_VALID_47_32    0x0e89

#define    RTL8367D_REG_IPMC_GROUP_VALID_63_48    0x0e8a

#define    RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL0    0x0e90
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL0_OFFSET    0
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL0_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL1    0x0e91
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL1_OFFSET    0
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL1_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL2    0x0e92
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL2_OFFSET    0
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL2_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL3    0x0e93
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL3_OFFSET    0
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL3_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL4    0x0e94
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL4_OFFSET    0
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL4_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL5    0x0e95
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL5_OFFSET    0
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL5_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL6    0x0e96
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL6_OFFSET    0
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL6_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL7    0x0e97
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL7_OFFSET    0
#define    RTL8367D_SVLAN_PORTBASED_SVID_CTRL7_MASK    0xFFF

/* (16'h0f00)hsactrl_reg */

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL0    0x0f00
#define    RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL1    0x0f01
#define    RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY1_CTRL0    0x0f02
#define    RTL8367D_SVLAN_SP2C_ENTRY1_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY1_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY1_CTRL1    0x0f03
#define    RTL8367D_SVLAN_SP2C_ENTRY1_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY1_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY1_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY1_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY2_CTRL0    0x0f04
#define    RTL8367D_SVLAN_SP2C_ENTRY2_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY2_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY2_CTRL1    0x0f05
#define    RTL8367D_SVLAN_SP2C_ENTRY2_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY2_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY2_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY2_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY3_CTRL0    0x0f06
#define    RTL8367D_SVLAN_SP2C_ENTRY3_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY3_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY3_CTRL1    0x0f07
#define    RTL8367D_SVLAN_SP2C_ENTRY3_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY3_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY3_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY3_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY4_CTRL0    0x0f08
#define    RTL8367D_SVLAN_SP2C_ENTRY4_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY4_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY4_CTRL1    0x0f09
#define    RTL8367D_SVLAN_SP2C_ENTRY4_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY4_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY4_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY4_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY5_CTRL0    0x0f0a
#define    RTL8367D_SVLAN_SP2C_ENTRY5_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY5_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY5_CTRL1    0x0f0b
#define    RTL8367D_SVLAN_SP2C_ENTRY5_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY5_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY5_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY5_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY6_CTRL0    0x0f0c
#define    RTL8367D_SVLAN_SP2C_ENTRY6_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY6_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY6_CTRL1    0x0f0d
#define    RTL8367D_SVLAN_SP2C_ENTRY6_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY6_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY6_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY6_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY7_CTRL0    0x0f0e
#define    RTL8367D_SVLAN_SP2C_ENTRY7_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY7_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY7_CTRL1    0x0f0f
#define    RTL8367D_SVLAN_SP2C_ENTRY7_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY7_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY7_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY7_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY8_CTRL0    0x0f10
#define    RTL8367D_SVLAN_SP2C_ENTRY8_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY8_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY8_CTRL1    0x0f11
#define    RTL8367D_SVLAN_SP2C_ENTRY8_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY8_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY8_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY8_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY9_CTRL0    0x0f12
#define    RTL8367D_SVLAN_SP2C_ENTRY9_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY9_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY9_CTRL1    0x0f13
#define    RTL8367D_SVLAN_SP2C_ENTRY9_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY9_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY9_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY9_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY10_CTRL0    0x0f14
#define    RTL8367D_SVLAN_SP2C_ENTRY10_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY10_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY10_CTRL1    0x0f15
#define    RTL8367D_SVLAN_SP2C_ENTRY10_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY10_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY10_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY10_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY11_CTRL0    0x0f16
#define    RTL8367D_SVLAN_SP2C_ENTRY11_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY11_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY11_CTRL1    0x0f17
#define    RTL8367D_SVLAN_SP2C_ENTRY11_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY11_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY11_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY11_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY12_CTRL0    0x0f18
#define    RTL8367D_SVLAN_SP2C_ENTRY12_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY12_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY12_CTRL1    0x0f19
#define    RTL8367D_SVLAN_SP2C_ENTRY12_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY12_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY12_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY12_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY13_CTRL0    0x0f1a
#define    RTL8367D_SVLAN_SP2C_ENTRY13_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY13_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY13_CTRL1    0x0f1b
#define    RTL8367D_SVLAN_SP2C_ENTRY13_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY13_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY13_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY13_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY14_CTRL0    0x0f1c
#define    RTL8367D_SVLAN_SP2C_ENTRY14_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY14_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY14_CTRL1    0x0f1d
#define    RTL8367D_SVLAN_SP2C_ENTRY14_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY14_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY14_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY14_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY15_CTRL0    0x0f1e
#define    RTL8367D_SVLAN_SP2C_ENTRY15_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY15_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY15_CTRL1    0x0f1f
#define    RTL8367D_SVLAN_SP2C_ENTRY15_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY15_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY15_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY15_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY16_CTRL0    0x0f20
#define    RTL8367D_SVLAN_SP2C_ENTRY16_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY16_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY16_CTRL1    0x0f21
#define    RTL8367D_SVLAN_SP2C_ENTRY16_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY16_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY16_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY16_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY17_CTRL0    0x0f22
#define    RTL8367D_SVLAN_SP2C_ENTRY17_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY17_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY17_CTRL1    0x0f23
#define    RTL8367D_SVLAN_SP2C_ENTRY17_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY17_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY17_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY17_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY18_CTRL0    0x0f24
#define    RTL8367D_SVLAN_SP2C_ENTRY18_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY18_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY18_CTRL1    0x0f25
#define    RTL8367D_SVLAN_SP2C_ENTRY18_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY18_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY18_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY18_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY19_CTRL0    0x0f26
#define    RTL8367D_SVLAN_SP2C_ENTRY19_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY19_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY19_CTRL1    0x0f27
#define    RTL8367D_SVLAN_SP2C_ENTRY19_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY19_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY19_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY19_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY20_CTRL0    0x0f28
#define    RTL8367D_SVLAN_SP2C_ENTRY20_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY20_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY20_CTRL1    0x0f29
#define    RTL8367D_SVLAN_SP2C_ENTRY20_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY20_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY20_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY20_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY21_CTRL0    0x0f2a
#define    RTL8367D_SVLAN_SP2C_ENTRY21_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY21_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY21_CTRL1    0x0f2b
#define    RTL8367D_SVLAN_SP2C_ENTRY21_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY21_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY21_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY21_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY22_CTRL0    0x0f2c
#define    RTL8367D_SVLAN_SP2C_ENTRY22_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY22_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY22_CTRL1    0x0f2d
#define    RTL8367D_SVLAN_SP2C_ENTRY22_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY22_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY22_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY22_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY23_CTRL0    0x0f2e
#define    RTL8367D_SVLAN_SP2C_ENTRY23_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY23_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY23_CTRL1    0x0f2f
#define    RTL8367D_SVLAN_SP2C_ENTRY23_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY23_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY23_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY23_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY24_CTRL0    0x0f30
#define    RTL8367D_SVLAN_SP2C_ENTRY24_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY24_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY24_CTRL1    0x0f31
#define    RTL8367D_SVLAN_SP2C_ENTRY24_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY24_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY24_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY24_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY25_CTRL0    0x0f32
#define    RTL8367D_SVLAN_SP2C_ENTRY25_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY25_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY25_CTRL1    0x0f33
#define    RTL8367D_SVLAN_SP2C_ENTRY25_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY25_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY25_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY25_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY26_CTRL0    0x0f34
#define    RTL8367D_SVLAN_SP2C_ENTRY26_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY26_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY26_CTRL1    0x0f35
#define    RTL8367D_SVLAN_SP2C_ENTRY26_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY26_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY26_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY26_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY27_CTRL0    0x0f36
#define    RTL8367D_SVLAN_SP2C_ENTRY27_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY27_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY27_CTRL1    0x0f37
#define    RTL8367D_SVLAN_SP2C_ENTRY27_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY27_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY27_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY27_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY28_CTRL0    0x0f38
#define    RTL8367D_SVLAN_SP2C_ENTRY28_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY28_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY28_CTRL1    0x0f39
#define    RTL8367D_SVLAN_SP2C_ENTRY28_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY28_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY28_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY28_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY29_CTRL0    0x0f3a
#define    RTL8367D_SVLAN_SP2C_ENTRY29_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY29_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY29_CTRL1    0x0f3b
#define    RTL8367D_SVLAN_SP2C_ENTRY29_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY29_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY29_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY29_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY30_CTRL0    0x0f3c
#define    RTL8367D_SVLAN_SP2C_ENTRY30_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY30_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY30_CTRL1    0x0f3d
#define    RTL8367D_SVLAN_SP2C_ENTRY30_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY30_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY30_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY30_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY31_CTRL0    0x0f3e
#define    RTL8367D_SVLAN_SP2C_ENTRY31_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY31_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY31_CTRL1    0x0f3f
#define    RTL8367D_SVLAN_SP2C_ENTRY31_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY31_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY31_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY31_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY32_CTRL0    0x0f40
#define    RTL8367D_SVLAN_SP2C_ENTRY32_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY32_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY32_CTRL1    0x0f41
#define    RTL8367D_SVLAN_SP2C_ENTRY32_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY32_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY32_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY32_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY33_CTRL0    0x0f42
#define    RTL8367D_SVLAN_SP2C_ENTRY33_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY33_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY33_CTRL1    0x0f43
#define    RTL8367D_SVLAN_SP2C_ENTRY33_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY33_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY33_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY33_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY34_CTRL0    0x0f44
#define    RTL8367D_SVLAN_SP2C_ENTRY34_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY34_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY34_CTRL1    0x0f45
#define    RTL8367D_SVLAN_SP2C_ENTRY34_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY34_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY34_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY34_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY35_CTRL0    0x0f46
#define    RTL8367D_SVLAN_SP2C_ENTRY35_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY35_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY35_CTRL1    0x0f47
#define    RTL8367D_SVLAN_SP2C_ENTRY35_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY35_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY35_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY35_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY36_CTRL0    0x0f48
#define    RTL8367D_SVLAN_SP2C_ENTRY36_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY36_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY36_CTRL1    0x0f49
#define    RTL8367D_SVLAN_SP2C_ENTRY36_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY36_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY36_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY36_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY37_CTRL0    0x0f4a
#define    RTL8367D_SVLAN_SP2C_ENTRY37_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY37_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY37_CTRL1    0x0f4b
#define    RTL8367D_SVLAN_SP2C_ENTRY37_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY37_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY37_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY37_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY38_CTRL0    0x0f4c
#define    RTL8367D_SVLAN_SP2C_ENTRY38_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY38_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY38_CTRL1    0x0f4d
#define    RTL8367D_SVLAN_SP2C_ENTRY38_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY38_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY38_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY38_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY39_CTRL0    0x0f4e
#define    RTL8367D_SVLAN_SP2C_ENTRY39_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY39_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY39_CTRL1    0x0f4f
#define    RTL8367D_SVLAN_SP2C_ENTRY39_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY39_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY39_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY39_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY40_CTRL0    0x0f50
#define    RTL8367D_SVLAN_SP2C_ENTRY40_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY40_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY40_CTRL1    0x0f51
#define    RTL8367D_SVLAN_SP2C_ENTRY40_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY40_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY40_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY40_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY41_CTRL0    0x0f52
#define    RTL8367D_SVLAN_SP2C_ENTRY41_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY41_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY41_CTRL1    0x0f53
#define    RTL8367D_SVLAN_SP2C_ENTRY41_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY41_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY41_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY41_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY42_CTRL0    0x0f54
#define    RTL8367D_SVLAN_SP2C_ENTRY42_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY42_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY42_CTRL1    0x0f55
#define    RTL8367D_SVLAN_SP2C_ENTRY42_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY42_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY42_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY42_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY43_CTRL0    0x0f56
#define    RTL8367D_SVLAN_SP2C_ENTRY43_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY43_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY43_CTRL1    0x0f57
#define    RTL8367D_SVLAN_SP2C_ENTRY43_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY43_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY43_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY43_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY44_CTRL0    0x0f58
#define    RTL8367D_SVLAN_SP2C_ENTRY44_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY44_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY44_CTRL1    0x0f59
#define    RTL8367D_SVLAN_SP2C_ENTRY44_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY44_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY44_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY44_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY45_CTRL0    0x0f5a
#define    RTL8367D_SVLAN_SP2C_ENTRY45_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY45_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY45_CTRL1    0x0f5b
#define    RTL8367D_SVLAN_SP2C_ENTRY45_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY45_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY45_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY45_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY46_CTRL0    0x0f5c
#define    RTL8367D_SVLAN_SP2C_ENTRY46_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY46_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY46_CTRL1    0x0f5d
#define    RTL8367D_SVLAN_SP2C_ENTRY46_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY46_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY46_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY46_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY47_CTRL0    0x0f5e
#define    RTL8367D_SVLAN_SP2C_ENTRY47_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY47_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY47_CTRL1    0x0f5f
#define    RTL8367D_SVLAN_SP2C_ENTRY47_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY47_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY47_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY47_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY48_CTRL0    0x0f60
#define    RTL8367D_SVLAN_SP2C_ENTRY48_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY48_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY48_CTRL1    0x0f61
#define    RTL8367D_SVLAN_SP2C_ENTRY48_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY48_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY48_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY48_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY49_CTRL0    0x0f62
#define    RTL8367D_SVLAN_SP2C_ENTRY49_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY49_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY49_CTRL1    0x0f63
#define    RTL8367D_SVLAN_SP2C_ENTRY49_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY49_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY49_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY49_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY50_CTRL0    0x0f64
#define    RTL8367D_SVLAN_SP2C_ENTRY50_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY50_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY50_CTRL1    0x0f65
#define    RTL8367D_SVLAN_SP2C_ENTRY50_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY50_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY50_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY50_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY51_CTRL0    0x0f66
#define    RTL8367D_SVLAN_SP2C_ENTRY51_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY51_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY51_CTRL1    0x0f67
#define    RTL8367D_SVLAN_SP2C_ENTRY51_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY51_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY51_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY51_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY52_CTRL0    0x0f68
#define    RTL8367D_SVLAN_SP2C_ENTRY52_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY52_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY52_CTRL1    0x0f69
#define    RTL8367D_SVLAN_SP2C_ENTRY52_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY52_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY52_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY52_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY53_CTRL0    0x0f6a
#define    RTL8367D_SVLAN_SP2C_ENTRY53_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY53_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY53_CTRL1    0x0f6b
#define    RTL8367D_SVLAN_SP2C_ENTRY53_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY53_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY53_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY53_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY54_CTRL0    0x0f6c
#define    RTL8367D_SVLAN_SP2C_ENTRY54_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY54_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY54_CTRL1    0x0f6d
#define    RTL8367D_SVLAN_SP2C_ENTRY54_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY54_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY54_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY54_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY55_CTRL0    0x0f6e
#define    RTL8367D_SVLAN_SP2C_ENTRY55_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY55_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY55_CTRL1    0x0f6f
#define    RTL8367D_SVLAN_SP2C_ENTRY55_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY55_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY55_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY55_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY56_CTRL0    0x0f70
#define    RTL8367D_SVLAN_SP2C_ENTRY56_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY56_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY56_CTRL1    0x0f71
#define    RTL8367D_SVLAN_SP2C_ENTRY56_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY56_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY56_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY56_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY57_CTRL0    0x0f72
#define    RTL8367D_SVLAN_SP2C_ENTRY57_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY57_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY57_CTRL1    0x0f73
#define    RTL8367D_SVLAN_SP2C_ENTRY57_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY57_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY57_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY57_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY58_CTRL0    0x0f74
#define    RTL8367D_SVLAN_SP2C_ENTRY58_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY58_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY58_CTRL1    0x0f75
#define    RTL8367D_SVLAN_SP2C_ENTRY58_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY58_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY58_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY58_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY59_CTRL0    0x0f76
#define    RTL8367D_SVLAN_SP2C_ENTRY59_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY59_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY59_CTRL1    0x0f77
#define    RTL8367D_SVLAN_SP2C_ENTRY59_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY59_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY59_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY59_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY60_CTRL0    0x0f78
#define    RTL8367D_SVLAN_SP2C_ENTRY60_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY60_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY60_CTRL1    0x0f79
#define    RTL8367D_SVLAN_SP2C_ENTRY60_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY60_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY60_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY60_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY61_CTRL0    0x0f7a
#define    RTL8367D_SVLAN_SP2C_ENTRY61_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY61_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY61_CTRL1    0x0f7b
#define    RTL8367D_SVLAN_SP2C_ENTRY61_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY61_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY61_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY61_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY62_CTRL0    0x0f7c
#define    RTL8367D_SVLAN_SP2C_ENTRY62_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY62_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY62_CTRL1    0x0f7d
#define    RTL8367D_SVLAN_SP2C_ENTRY62_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY62_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY62_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY62_CTRL1_VID_MASK    0xFFF

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY63_CTRL0    0x0f7e
#define    RTL8367D_SVLAN_SP2C_ENTRY63_CTRL0_SVID_OFFSET    3
#define    RTL8367D_SVLAN_SP2C_ENTRY63_CTRL0_SVID_MASK    0x7FF8
#define    RTL8367D_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_MASK    0x7

#define    RTL8367D_REG_SVLAN_SP2C_ENTRY63_CTRL1    0x0f7f
#define    RTL8367D_SVLAN_SP2C_ENTRY63_CTRL1_VALID_OFFSET    12
#define    RTL8367D_SVLAN_SP2C_ENTRY63_CTRL1_VALID_MASK    0x1000
#define    RTL8367D_SVLAN_SP2C_ENTRY63_CTRL1_VID_OFFSET    0
#define    RTL8367D_SVLAN_SP2C_ENTRY63_CTRL1_VID_MASK    0xFFF

/* (16'h1000)mib_reg */

#define    RTL8367D_REG_MIB_COUNTER0    0x1000

#define    RTL8367D_REG_MIB_COUNTER1    0x1001

#define    RTL8367D_REG_MIB_COUNTER2    0x1002

#define    RTL8367D_REG_MIB_COUNTER3    0x1003

#define    RTL8367D_REG_MIB_ADDRESS    0x1004
#define    RTL8367D_MIB_ADDRESS_OFFSET    0
#define    RTL8367D_MIB_ADDRESS_MASK    0x1FF

#define    RTL8367D_REG_MIB_CTRL0    0x1005
#define    RTL8367D_RESET_VALUE_OFFSET    12
#define    RTL8367D_RESET_VALUE_MASK    0x1000
#define    RTL8367D_GLOBAL_RESET_OFFSET    11
#define    RTL8367D_GLOBAL_RESET_MASK    0x800
#define    RTL8367D_QM_RESET_OFFSET    10
#define    RTL8367D_QM_RESET_MASK    0x400
#define    RTL8367D_PORT7_RESET_OFFSET    9
#define    RTL8367D_PORT7_RESET_MASK    0x200
#define    RTL8367D_PORT6_RESET_OFFSET    8
#define    RTL8367D_PORT6_RESET_MASK    0x100
#define    RTL8367D_PORT5_RESET_OFFSET    7
#define    RTL8367D_PORT5_RESET_MASK    0x80
#define    RTL8367D_PORT4_RESET_OFFSET    6
#define    RTL8367D_PORT4_RESET_MASK    0x40
#define    RTL8367D_PORT3_RESET_OFFSET    5
#define    RTL8367D_PORT3_RESET_MASK    0x20
#define    RTL8367D_PORT2_RESET_OFFSET    4
#define    RTL8367D_PORT2_RESET_MASK    0x10
#define    RTL8367D_PORT1_RESET_OFFSET    3
#define    RTL8367D_PORT1_RESET_MASK    0x8
#define    RTL8367D_PORT0_RESET_OFFSET    2
#define    RTL8367D_PORT0_RESET_MASK    0x4
#define    RTL8367D_RESET_FLAG_OFFSET    1
#define    RTL8367D_RESET_FLAG_MASK    0x2
#define    RTL8367D_MIB_CTRL0_BUSY_FLAG_OFFSET    0
#define    RTL8367D_MIB_CTRL0_BUSY_FLAG_MASK    0x1

#define    RTL8367D_REG_MIB_CTRL1    0x1007
#define    RTL8367D_COUNTER15_RESET_OFFSET    15
#define    RTL8367D_COUNTER15_RESET_MASK    0x8000
#define    RTL8367D_COUNTER14_RESET_OFFSET    14
#define    RTL8367D_COUNTER14_RESET_MASK    0x4000
#define    RTL8367D_COUNTER13_RESET_OFFSET    13
#define    RTL8367D_COUNTER13_RESET_MASK    0x2000
#define    RTL8367D_COUNTER12_RESET_OFFSET    12
#define    RTL8367D_COUNTER12_RESET_MASK    0x1000
#define    RTL8367D_COUNTER11_RESET_OFFSET    11
#define    RTL8367D_COUNTER11_RESET_MASK    0x800
#define    RTL8367D_COUNTER10_RESET_OFFSET    10
#define    RTL8367D_COUNTER10_RESET_MASK    0x400
#define    RTL8367D_COUNTER9_RESET_OFFSET    9
#define    RTL8367D_COUNTER9_RESET_MASK    0x200
#define    RTL8367D_COUNTER8_RESET_OFFSET    8
#define    RTL8367D_COUNTER8_RESET_MASK    0x100
#define    RTL8367D_COUNTER7_RESET_OFFSET    7
#define    RTL8367D_COUNTER7_RESET_MASK    0x80
#define    RTL8367D_COUNTER6_RESET_OFFSET    6
#define    RTL8367D_COUNTER6_RESET_MASK    0x40
#define    RTL8367D_COUNTER5_RESET_OFFSET    5
#define    RTL8367D_COUNTER5_RESET_MASK    0x20
#define    RTL8367D_COUNTER4_RESET_OFFSET    4
#define    RTL8367D_COUNTER4_RESET_MASK    0x10
#define    RTL8367D_COUNTER3_RESET_OFFSET    3
#define    RTL8367D_COUNTER3_RESET_MASK    0x8
#define    RTL8367D_COUNTER2_RESET_OFFSET    2
#define    RTL8367D_COUNTER2_RESET_MASK    0x4
#define    RTL8367D_COUNTER1_RESET_OFFSET    1
#define    RTL8367D_COUNTER1_RESET_MASK    0x2
#define    RTL8367D_COUNTER0_RESET_OFFSET    0
#define    RTL8367D_COUNTER0_RESET_MASK    0x1

#define    RTL8367D_REG_MIB_CTRL3    0x1009
#define    RTL8367D_COUNTER7_MODE_OFFSET    7
#define    RTL8367D_COUNTER7_MODE_MASK    0x80
#define    RTL8367D_COUNTER6_MODE_OFFSET    6
#define    RTL8367D_COUNTER6_MODE_MASK    0x40
#define    RTL8367D_COUNTER5_MODE_OFFSET    5
#define    RTL8367D_COUNTER5_MODE_MASK    0x20
#define    RTL8367D_COUNTER4_MODE_OFFSET    4
#define    RTL8367D_COUNTER4_MODE_MASK    0x10
#define    RTL8367D_COUNTER3_MODE_OFFSET    3
#define    RTL8367D_COUNTER3_MODE_MASK    0x8
#define    RTL8367D_COUNTER2_MODE_OFFSET    2
#define    RTL8367D_COUNTER2_MODE_MASK    0x4
#define    RTL8367D_COUNTER1_MODE_OFFSET    1
#define    RTL8367D_COUNTER1_MODE_MASK    0x2
#define    RTL8367D_COUNTER0_MODE_OFFSET    0
#define    RTL8367D_COUNTER0_MODE_MASK    0x1

#define    RTL8367D_REG_MIB_CTRL4    0x100a
#define    RTL8367D_MIB_USAGE_MODE_OFFSET    8
#define    RTL8367D_MIB_USAGE_MODE_MASK    0x100
#define    RTL8367D_MIB_TIMER_OFFSET    0
#define    RTL8367D_MIB_TIMER_MASK    0xFF

#define    RTL8367D_REG_MIB_CTRL5    0x100b
#define    RTL8367D_COUNTER7_TYPE_OFFSET    7
#define    RTL8367D_COUNTER7_TYPE_MASK    0x80
#define    RTL8367D_COUNTER6_TYPE_OFFSET    6
#define    RTL8367D_COUNTER6_TYPE_MASK    0x40
#define    RTL8367D_COUNTER5_TYPE_OFFSET    5
#define    RTL8367D_COUNTER5_TYPE_MASK    0x20
#define    RTL8367D_COUNTER4_TYPE_OFFSET    4
#define    RTL8367D_COUNTER4_TYPE_MASK    0x10
#define    RTL8367D_COUNTER3_TYPE_OFFSET    3
#define    RTL8367D_COUNTER3_TYPE_MASK    0x8
#define    RTL8367D_COUNTER2_TYPE_OFFSET    2
#define    RTL8367D_COUNTER2_TYPE_MASK    0x4
#define    RTL8367D_COUNTER1_TYPE_OFFSET    1
#define    RTL8367D_COUNTER1_TYPE_MASK    0x2
#define    RTL8367D_COUNTER0_TYPE_OFFSET    0
#define    RTL8367D_COUNTER0_TYPE_MASK    0x1

/* (16'h1100)intrpt_reg */

#define    RTL8367D_REG_INTR_CTRL    0x1100
#define    RTL8367D_CFG_INT_TM_NEG_OFFSET    1
#define    RTL8367D_CFG_INT_TM_NEG_MASK    0x2
#define    RTL8367D_INTR_POLARITY_OFFSET    0
#define    RTL8367D_INTR_POLARITY_MASK    0x1

#define    RTL8367D_REG_INTR_IMR    0x1101
#define    RTL8367D_INTR_IMR_THERMAL_ALARM_OFFSET    12
#define    RTL8367D_INTR_IMR_THERMAL_ALARM_MASK    0x1000
#define    RTL8367D_INTR_IMR_SLIENT_START_OFFSET    11
#define    RTL8367D_INTR_IMR_SLIENT_START_MASK    0x800
#define    RTL8367D_INTR_IMR_ACL_ACTION_OFFSET    9
#define    RTL8367D_INTR_IMR_ACL_ACTION_MASK    0x200
#define    RTL8367D_INTR_IMR_CABLE_DIAG_FIN_OFFSET    8
#define    RTL8367D_INTR_IMR_CABLE_DIAG_FIN_MASK    0x100
#define    RTL8367D_INTR_IMR_INTERRUPT_8051_OFFSET    7
#define    RTL8367D_INTR_IMR_INTERRUPT_8051_MASK    0x80
#define    RTL8367D_INTR_IMR_LOOP_DETECTION_OFFSET    6
#define    RTL8367D_INTR_IMR_LOOP_DETECTION_MASK    0x40
#define    RTL8367D_INTR_IMR_SPECIAL_CONGEST_OFFSET    4
#define    RTL8367D_INTR_IMR_SPECIAL_CONGEST_MASK    0x10
#define    RTL8367D_INTR_IMR_SPEED_CHANGE_OFFSET    3
#define    RTL8367D_INTR_IMR_SPEED_CHANGE_MASK    0x8
#define    RTL8367D_INTR_IMR_LEARN_OVER_OFFSET    2
#define    RTL8367D_INTR_IMR_LEARN_OVER_MASK    0x4
#define    RTL8367D_INTR_IMR_METER_EXCEEDED_OFFSET    1
#define    RTL8367D_INTR_IMR_METER_EXCEEDED_MASK    0x2
#define    RTL8367D_INTR_IMR_LINK_CHANGE_OFFSET    0
#define    RTL8367D_INTR_IMR_LINK_CHANGE_MASK    0x1

#define    RTL8367D_REG_INTR_IMS    0x1102
#define    RTL8367D_INTR_IMS_THERMAL_ALARM_OFFSET    12
#define    RTL8367D_INTR_IMS_THERMAL_ALARM_MASK    0x1000
#define    RTL8367D_INTR_IMS_SLIENT_START_OFFSET    11
#define    RTL8367D_INTR_IMS_SLIENT_START_MASK    0x800
#define    RTL8367D_INTR_IMS_ACL_ACTION_OFFSET    9
#define    RTL8367D_INTR_IMS_ACL_ACTION_MASK    0x200
#define    RTL8367D_INTR_IMS_CABLE_DIAG_FIN_OFFSET    8
#define    RTL8367D_INTR_IMS_CABLE_DIAG_FIN_MASK    0x100
#define    RTL8367D_INTR_IMS_INTERRUPT_8051_OFFSET    7
#define    RTL8367D_INTR_IMS_INTERRUPT_8051_MASK    0x80
#define    RTL8367D_INTR_IMS_LOOP_DETECTION_OFFSET    6
#define    RTL8367D_INTR_IMS_LOOP_DETECTION_MASK    0x40
#define    RTL8367D_INTR_IMS_SPECIAL_CONGEST_OFFSET    4
#define    RTL8367D_INTR_IMS_SPECIAL_CONGEST_MASK    0x10
#define    RTL8367D_INTR_IMS_SPEED_CHANGE_OFFSET    3
#define    RTL8367D_INTR_IMS_SPEED_CHANGE_MASK    0x8
#define    RTL8367D_INTR_IMS_LEARN_OVER_OFFSET    2
#define    RTL8367D_INTR_IMS_LEARN_OVER_MASK    0x4
#define    RTL8367D_INTR_IMS_METER_EXCEEDED_OFFSET    1
#define    RTL8367D_INTR_IMS_METER_EXCEEDED_MASK    0x2
#define    RTL8367D_INTR_IMS_LINK_CHANGE_OFFSET    0
#define    RTL8367D_INTR_IMS_LINK_CHANGE_MASK    0x1

#define    RTL8367D_REG_LEARN_OVER_INDICATOR    0x1103
#define    RTL8367D_LEARN_OVER_INDICATOR_OFFSET    0
#define    RTL8367D_LEARN_OVER_INDICATOR_MASK    0xFF

#define    RTL8367D_REG_SPEED_CHANGE_INDICATOR    0x1104
#define    RTL8367D_SPEED_CHANGE_INDICATOR_OFFSET    0
#define    RTL8367D_SPEED_CHANGE_INDICATOR_MASK    0xFF

#define    RTL8367D_REG_SPECIAL_CONGEST_INDICATOR    0x1105
#define    RTL8367D_SPECIAL_CONGEST_INDICATOR_OFFSET    0
#define    RTL8367D_SPECIAL_CONGEST_INDICATOR_MASK    0xFF

#define    RTL8367D_REG_PORT_LINKDOWN_INDICATOR    0x1106
#define    RTL8367D_PORT_LINKDOWN_INDICATOR_OFFSET    0
#define    RTL8367D_PORT_LINKDOWN_INDICATOR_MASK    0xFF

#define    RTL8367D_REG_PORT_LINKUP_INDICATOR    0x1107
#define    RTL8367D_PORT_LINKUP_INDICATOR_OFFSET    0
#define    RTL8367D_PORT_LINKUP_INDICATOR_MASK    0xFF

#define    RTL8367D_REG_SYSTEM_LEARN_OVER_INDICATOR    0x1108
#define    RTL8367D_SYSTEM_LEARN_OVER_INDICATOR_OFFSET    0
#define    RTL8367D_SYSTEM_LEARN_OVER_INDICATOR_MASK    0x1

#define    RTL8367D_REG_THERMAL_ALARM_INDICATOR    0x1109
#define    RTL8367D_THERMAL_ALARM_INDICATOR_OFFSET    0
#define    RTL8367D_THERMAL_ALARM_INDICATOR_MASK    0xF

#define    RTL8367D_REG_INTR_IMR_8051    0x1118
#define    RTL8367D_INTR_IMR_8051_THERMAL_ALARM_OFFSET    13
#define    RTL8367D_INTR_IMR_8051_THERMAL_ALARM_MASK    0x2000
#define    RTL8367D_INTR_IMR_8051_SLIENT_START_OFFSET    12
#define    RTL8367D_INTR_IMR_8051_SLIENT_START_MASK    0x1000
#define    RTL8367D_INTR_IMR_8051_ACL_ACTION_OFFSET    10
#define    RTL8367D_INTR_IMR_8051_ACL_ACTION_MASK    0x400
#define    RTL8367D_INTR_IMR_8051_SAMOVING_8051_OFFSET    9
#define    RTL8367D_INTR_IMR_8051_SAMOVING_8051_MASK    0x200
#define    RTL8367D_INTR_IMR_8051_CABLE_DIAG_FIN_8051_OFFSET    8
#define    RTL8367D_INTR_IMR_8051_CABLE_DIAG_FIN_8051_MASK    0x100
#define    RTL8367D_INTR_IMR_8051_LOOP_DETECTION_8051_OFFSET    6
#define    RTL8367D_INTR_IMR_8051_LOOP_DETECTION_8051_MASK    0x40
#define    RTL8367D_INTR_IMR_8051_SPECIAL_CONGEST_8051_OFFSET    4
#define    RTL8367D_INTR_IMR_8051_SPECIAL_CONGEST_8051_MASK    0x10
#define    RTL8367D_INTR_IMR_8051_SPEED_CHANGE_8051_OFFSET    3
#define    RTL8367D_INTR_IMR_8051_SPEED_CHANGE_8051_MASK    0x8
#define    RTL8367D_INTR_IMR_8051_LEARN_OVER_8051_OFFSET    2
#define    RTL8367D_INTR_IMR_8051_LEARN_OVER_8051_MASK    0x4
#define    RTL8367D_INTR_IMR_8051_METER_EXCEEDED_8051_OFFSET    1
#define    RTL8367D_INTR_IMR_8051_METER_EXCEEDED_8051_MASK    0x2
#define    RTL8367D_INTR_IMR_8051_LINK_CHANGE_8051_OFFSET    0
#define    RTL8367D_INTR_IMR_8051_LINK_CHANGE_8051_MASK    0x1

#define    RTL8367D_REG_INTR_IMS_8051    0x1119
#define    RTL8367D_INTR_IMS_8051_THERMAL_ALARM_OFFSET    13
#define    RTL8367D_INTR_IMS_8051_THERMAL_ALARM_MASK    0x2000
#define    RTL8367D_INTR_IMS_8051_SLIENT_START_OFFSET    12
#define    RTL8367D_INTR_IMS_8051_SLIENT_START_MASK    0x1000
#define    RTL8367D_INTR_IMS_8051_ACL_ACTION_OFFSET    10
#define    RTL8367D_INTR_IMS_8051_ACL_ACTION_MASK    0x400
#define    RTL8367D_INTR_IMS_8051_SAMOVING_8051_OFFSET    9
#define    RTL8367D_INTR_IMS_8051_SAMOVING_8051_MASK    0x200
#define    RTL8367D_INTR_IMS_8051_CABLE_DIAG_FIN_8051_OFFSET    8
#define    RTL8367D_INTR_IMS_8051_CABLE_DIAG_FIN_8051_MASK    0x100
#define    RTL8367D_INTR_IMS_8051_LOOP_DETECTION_8051_OFFSET    6
#define    RTL8367D_INTR_IMS_8051_LOOP_DETECTION_8051_MASK    0x40
#define    RTL8367D_INTR_IMS_8051_SPECIAL_CONGEST_8051_OFFSET    4
#define    RTL8367D_INTR_IMS_8051_SPECIAL_CONGEST_8051_MASK    0x10
#define    RTL8367D_INTR_IMS_8051_SPEED_CHANGE_8051_OFFSET    3
#define    RTL8367D_INTR_IMS_8051_SPEED_CHANGE_8051_MASK    0x8
#define    RTL8367D_INTR_IMS_8051_LEARN_OVER_8051_OFFSET    2
#define    RTL8367D_INTR_IMS_8051_LEARN_OVER_8051_MASK    0x4
#define    RTL8367D_INTR_IMS_8051_METER_EXCEEDED_8051_OFFSET    1
#define    RTL8367D_INTR_IMS_8051_METER_EXCEEDED_8051_MASK    0x2
#define    RTL8367D_INTR_IMS_8051_LINK_CHANGE_8051_OFFSET    0
#define    RTL8367D_INTR_IMS_8051_LINK_CHANGE_8051_MASK    0x1

#define    RTL8367D_REG_DW8051_INT_CPU    0x111a
#define    RTL8367D_DW8051_INT_CPU_OFFSET    0
#define    RTL8367D_DW8051_INT_CPU_MASK    0x1

#define    RTL8367D_REG_LEARN_OVER_INDICATOR_8051    0x1120
#define    RTL8367D_LEARN_OVER_INDICATOR_8051_OFFSET    0
#define    RTL8367D_LEARN_OVER_INDICATOR_8051_MASK    0xFF

#define    RTL8367D_REG_SPEED_CHANGE_INDICATOR_8051    0x1121
#define    RTL8367D_SPEED_CHANGE_INDICATOR_8051_OFFSET    0
#define    RTL8367D_SPEED_CHANGE_INDICATOR_8051_MASK    0xFF

#define    RTL8367D_REG_SPECIAL_CONGEST_INDICATOR_8051    0x1122
#define    RTL8367D_SPECIAL_CONGEST_INDICATOR_8051_OFFSET    0
#define    RTL8367D_SPECIAL_CONGEST_INDICATOR_8051_MASK    0xFF

#define    RTL8367D_REG_PORT_LINKDOWN_INDICATOR_8051    0x1123
#define    RTL8367D_PORT_LINKDOWN_INDICATOR_8051_OFFSET    0
#define    RTL8367D_PORT_LINKDOWN_INDICATOR_8051_MASK    0xFF

#define    RTL8367D_REG_PORT_LINKUP_INDICATOR_8051    0x1124
#define    RTL8367D_PORT_LINKUP_INDICATOR_8051_OFFSET    0
#define    RTL8367D_PORT_LINKUP_INDICATOR_8051_MASK    0xFF

#define    RTL8367D_REG_THERMAL_ALARM_INDICATOR_8051    0x1125
#define    RTL8367D_THERMAL_ALARM_INDICATOR_8051_OFFSET    0
#define    RTL8367D_THERMAL_ALARM_INDICATOR_8051_MASK    0xF

#define    RTL8367D_REG_INTR_IMS_BUFFER_RESET    0x112a
#define    RTL8367D_INTR_IMS_BUFFER_RESET_IMR_BUFF_RESET_OFFSET    1
#define    RTL8367D_INTR_IMS_BUFFER_RESET_IMR_BUFF_RESET_MASK    0x2
#define    RTL8367D_INTR_IMS_BUFFER_RESET_BUFFER_RESET_OFFSET    0
#define    RTL8367D_INTR_IMS_BUFFER_RESET_BUFFER_RESET_MASK    0x1

#define    RTL8367D_REG_INTR_IMS_8051_BUFFER_RESET    0x112b
#define    RTL8367D_INTR_IMS_8051_BUFFER_RESET_IMR_BUFF_RESET_OFFSET    1
#define    RTL8367D_INTR_IMS_8051_BUFFER_RESET_IMR_BUFF_RESET_MASK    0x2
#define    RTL8367D_INTR_IMS_8051_BUFFER_RESET_BUFFER_RESET_OFFSET    0
#define    RTL8367D_INTR_IMS_8051_BUFFER_RESET_BUFFER_RESET_MASK    0x1

#define    RTL8367D_REG_GPHY_INTRPT_8051    0x112c
#define    RTL8367D_IMS_GPHY_8051_OFFSET    5
#define    RTL8367D_IMS_GPHY_8051_MASK    0x3E0
#define    RTL8367D_IMR_GPHY_8051_OFFSET    0
#define    RTL8367D_IMR_GPHY_8051_MASK    0x1F

#define    RTL8367D_REG_GPHY_INTRPT    0x112d
#define    RTL8367D_IMS_GPHY_OFFSET    5
#define    RTL8367D_IMS_GPHY_MASK    0x3E0
#define    RTL8367D_IMR_GPHY_OFFSET    0
#define    RTL8367D_IMR_GPHY_MASK    0x1F

/* (16'h1200)swcore_reg */

#define    RTL8367D_REG_MAX_LENGTH_LIMINT_IPG    0x1200
#define    RTL8367D_EGSFC_SHARE_PKT_THRESHOLD_OFFSET    6
#define    RTL8367D_EGSFC_SHARE_PKT_THRESHOLD_MASK    0x1FC0
#define    RTL8367D_CHECK_MIN_IPG_RXDV_OFFSET    5
#define    RTL8367D_CHECK_MIN_IPG_RXDV_MASK    0x20
#define    RTL8367D_LIMIT_IPG_CFG_OFFSET    0
#define    RTL8367D_LIMIT_IPG_CFG_MASK    0x1F

#define    RTL8367D_REG_IOL_RXDROP_CFG    0x1201
#define    RTL8367D_RX_IOL_MAX_LENGTH_CFG_OFFSET    13
#define    RTL8367D_RX_IOL_MAX_LENGTH_CFG_MASK    0x2000
#define    RTL8367D_RX_IOL_ERROR_LENGTH_CFG_OFFSET    12
#define    RTL8367D_RX_IOL_ERROR_LENGTH_CFG_MASK    0x1000
#define    RTL8367D_RX_NODROP_PAUSE_CFG_OFFSET    8
#define    RTL8367D_RX_NODROP_PAUSE_CFG_MASK    0x100
#define    RTL8367D_RX_DV_CNT_CFG_OFFSET    0
#define    RTL8367D_RX_DV_CNT_CFG_MASK    0x3F

#define    RTL8367D_REG_VS_TPID    0x1202

#define    RTL8367D_REG_INBW_HBOUND    0x1203
#define    RTL8367D_INBW_HBOUND_OFFSET    0
#define    RTL8367D_INBW_HBOUND_MASK    0xFF

#define    RTL8367D_REG_CFG_TX_ITFSP_OP    0x1204
#define    RTL8367D_MASK_OFFSET    1
#define    RTL8367D_MASK_MASK    0x2
#define    RTL8367D_OP_OFFSET    0
#define    RTL8367D_OP_MASK    0x1

#define    RTL8367D_REG_INBW_LBOUND    0x1205
#define    RTL8367D_INBW_LBOUND_OFFSET    0
#define    RTL8367D_INBW_LBOUND_MASK    0xFF

#define    RTL8367D_REG_CFG_48PASS1_DROP    0x1206
#define    RTL8367D_CFG_48PASS1_DROP_OFFSET    0
#define    RTL8367D_CFG_48PASS1_DROP_MASK    0x1

#define    RTL8367D_REG_CFG_BACKPRESSURE    0x1207
#define    RTL8367D_LONGTXE_OFFSET    12
#define    RTL8367D_LONGTXE_MASK    0x1000
#define    RTL8367D_EN_BYPASS_ERROR_OFFSET    8
#define    RTL8367D_EN_BYPASS_ERROR_MASK    0x100
#define    RTL8367D_EN_BACKPRESSURE_OFFSET    4
#define    RTL8367D_EN_BACKPRESSURE_MASK    0x10
#define    RTL8367D_EN_48_PASS_1_OFFSET    0
#define    RTL8367D_EN_48_PASS_1_MASK    0x1

#define    RTL8367D_REG_CFG_UNHIOL    0x1208
#define    RTL8367D_IOL_BACKOFF_OFFSET    12
#define    RTL8367D_IOL_BACKOFF_MASK    0x1000
#define    RTL8367D_BACKOFF_RANDOM_TIME_OFFSET    8
#define    RTL8367D_BACKOFF_RANDOM_TIME_MASK    0x100
#define    RTL8367D_DISABLE_BACK_OFF_OFFSET    4
#define    RTL8367D_DISABLE_BACK_OFF_MASK    0x10
#define    RTL8367D_IPG_COMPENSATION_OFFSET    0
#define    RTL8367D_IPG_COMPENSATION_MASK    0x1

#define    RTL8367D_REG_SWITCH_MAC0    0x1209

#define    RTL8367D_REG_SWITCH_MAC1    0x120a

#define    RTL8367D_REG_SWITCH_MAC2    0x120b

#define    RTL8367D_REG_SWITCH_CTRL0    0x120c
#define    RTL8367D_PORT7_REMARKING_DSCP_ENABLE_OFFSET    15
#define    RTL8367D_PORT7_REMARKING_DSCP_ENABLE_MASK    0x8000
#define    RTL8367D_PORT6_REMARKING_DSCP_ENABLE_OFFSET    14
#define    RTL8367D_PORT6_REMARKING_DSCP_ENABLE_MASK    0x4000
#define    RTL8367D_PORT5_REMARKING_DSCP_ENABLE_OFFSET    13
#define    RTL8367D_PORT5_REMARKING_DSCP_ENABLE_MASK    0x2000
#define    RTL8367D_PORT4_REMARKING_DSCP_ENABLE_OFFSET    12
#define    RTL8367D_PORT4_REMARKING_DSCP_ENABLE_MASK    0x1000
#define    RTL8367D_PORT3_REMARKING_DSCP_ENABLE_OFFSET    11
#define    RTL8367D_PORT3_REMARKING_DSCP_ENABLE_MASK    0x800
#define    RTL8367D_PORT2_REMARKING_DSCP_ENABLE_OFFSET    10
#define    RTL8367D_PORT2_REMARKING_DSCP_ENABLE_MASK    0x400
#define    RTL8367D_PORT1_REMARKING_DSCP_ENABLE_OFFSET    9
#define    RTL8367D_PORT1_REMARKING_DSCP_ENABLE_MASK    0x200
#define    RTL8367D_PORT0_REMARKING_DSCP_ENABLE_OFFSET    8
#define    RTL8367D_PORT0_REMARKING_DSCP_ENABLE_MASK    0x100
#define    RTL8367D_SHORT_IPG_OFFSET    4
#define    RTL8367D_SHORT_IPG_MASK    0x10
#define    RTL8367D_PAUSE_MAX128_OFFSET    0
#define    RTL8367D_PAUSE_MAX128_MASK    0x1

#define    RTL8367D_REG_QOS_DSCP_REMARK_CTRL0    0x120d
#define    RTL8367D_INTPRI1_DSCP_OFFSET    8
#define    RTL8367D_INTPRI1_DSCP_MASK    0x3F00
#define    RTL8367D_INTPRI0_DSCP_OFFSET    0
#define    RTL8367D_INTPRI0_DSCP_MASK    0x3F

#define    RTL8367D_REG_QOS_DSCP_REMARK_CTRL1    0x120e
#define    RTL8367D_INTPRI3_DSCP_OFFSET    8
#define    RTL8367D_INTPRI3_DSCP_MASK    0x3F00
#define    RTL8367D_INTPRI2_DSCP_OFFSET    0
#define    RTL8367D_INTPRI2_DSCP_MASK    0x3F

#define    RTL8367D_REG_QOS_DSCP_REMARK_CTRL2    0x120f
#define    RTL8367D_INTPRI5_DSCP_OFFSET    8
#define    RTL8367D_INTPRI5_DSCP_MASK    0x3F00
#define    RTL8367D_INTPRI4_DSCP_OFFSET    0
#define    RTL8367D_INTPRI4_DSCP_MASK    0x3F

#define    RTL8367D_REG_QOS_DSCP_REMARK_CTRL3    0x1210
#define    RTL8367D_INTPRI7_DSCP_OFFSET    8
#define    RTL8367D_INTPRI7_DSCP_MASK    0x3F00
#define    RTL8367D_INTPRI6_DSCP_OFFSET    0
#define    RTL8367D_INTPRI6_DSCP_MASK    0x3F

#define    RTL8367D_REG_QOS_1Q_REMARK_CTRL0    0x1211
#define    RTL8367D_INTPRI3_PRI_OFFSET    12
#define    RTL8367D_INTPRI3_PRI_MASK    0x7000
#define    RTL8367D_INTPRI2_PRI_OFFSET    8
#define    RTL8367D_INTPRI2_PRI_MASK    0x700
#define    RTL8367D_INTPRI1_PRI_OFFSET    4
#define    RTL8367D_INTPRI1_PRI_MASK    0x70
#define    RTL8367D_INTPRI0_PRI_OFFSET    0
#define    RTL8367D_INTPRI0_PRI_MASK    0x7

#define    RTL8367D_REG_QOS_1Q_REMARK_CTRL1    0x1212
#define    RTL8367D_INTPRI7_PRI_OFFSET    12
#define    RTL8367D_INTPRI7_PRI_MASK    0x7000
#define    RTL8367D_INTPRI6_PRI_OFFSET    8
#define    RTL8367D_INTPRI6_PRI_MASK    0x700
#define    RTL8367D_INTPRI5_PRI_OFFSET    4
#define    RTL8367D_INTPRI5_PRI_MASK    0x70
#define    RTL8367D_INTPRI4_PRI_OFFSET    0
#define    RTL8367D_INTPRI4_PRI_MASK    0x7

#define    RTL8367D_REG_PKTGEN_COMMAND    0x1213
#define    RTL8367D_PKTGEN_STOP_OFFSET    8
#define    RTL8367D_PKTGEN_STOP_MASK    0x100
#define    RTL8367D_PKTGEN_START_OFFSET    4
#define    RTL8367D_PKTGEN_START_MASK    0x10
#define    RTL8367D_PKTGEN_BYPASS_FLOWCONTROL_OFFSET    0
#define    RTL8367D_PKTGEN_BYPASS_FLOWCONTROL_MASK    0x1

#define    RTL8367D_REG_SW_DUMMY0    0x1214
#define    RTL8367D_SW_DUMMY0_DUMMY_OFFSET    4
#define    RTL8367D_SW_DUMMY0_DUMMY_MASK    0xFFF0
#define    RTL8367D_EEE_DEFER_TXLPI_OFFSET    3
#define    RTL8367D_EEE_DEFER_TXLPI_MASK    0x8
#define    RTL8367D_INGRESSBW_BYPASS_EN_OFFSET    2
#define    RTL8367D_INGRESSBW_BYPASS_EN_MASK    0x4
#define    RTL8367D_CFG_RX_MIN_OFFSET    0
#define    RTL8367D_CFG_RX_MIN_MASK    0x3

#define    RTL8367D_REG_SW_DUMMY1    0x1215

#define    RTL8367D_REG_PKTGEN_PAUSE_TIME    0x1216

#define    RTL8367D_REG_SVLAN_UPLINK_PORTMASK    0x1218
#define    RTL8367D_SVLAN_UPLINK_PORTMASK_OFFSET    0
#define    RTL8367D_SVLAN_UPLINK_PORTMASK_MASK    0xFF

#define    RTL8367D_REG_CPU_PORT_MASK    0x1219
#define    RTL8367D_CPU_PORT_MASK_OFFSET    0
#define    RTL8367D_CPU_PORT_MASK_MASK    0xFF

#define    RTL8367D_REG_CPU_CTRL    0x121a
#define    RTL8367D_CPU_TAG_FORMAT_PRI_OFFSET    10
#define    RTL8367D_CPU_TAG_FORMAT_PRI_MASK    0x400
#define    RTL8367D_CPU_TAG_FORMAT_OFFSET    9
#define    RTL8367D_CPU_TAG_FORMAT_MASK    0x200
#define    RTL8367D_IOL_16DROP_OFFSET    8
#define    RTL8367D_IOL_16DROP_MASK    0x100
#define    RTL8367D_CPU_TAG_RXBYTECOUNT_OFFSET    7
#define    RTL8367D_CPU_TAG_RXBYTECOUNT_MASK    0x80
#define    RTL8367D_CPU_TAG_POSITION_OFFSET    6
#define    RTL8367D_CPU_TAG_POSITION_MASK    0x40
#define    RTL8367D_CPU_TRAP_PORT_OFFSET    3
#define    RTL8367D_CPU_TRAP_PORT_MASK    0x38
#define    RTL8367D_CPU_INSERTMODE_OFFSET    1
#define    RTL8367D_CPU_INSERTMODE_MASK    0x6
#define    RTL8367D_CPU_EN_OFFSET    0
#define    RTL8367D_CPU_EN_MASK    0x1

#define    RTL8367D_REG_MIRROR_CTRL    0x121c
#define    RTL8367D_MIRROR_CTRL_DUMMY_OFFSET    12
#define    RTL8367D_MIRROR_CTRL_DUMMY_MASK    0xF000
#define    RTL8367D_MIRROR_ISO_OFFSET    11
#define    RTL8367D_MIRROR_ISO_MASK    0x800
#define    RTL8367D_MIRROR_MONITOR_PORT_OFFSET    4
#define    RTL8367D_MIRROR_MONITOR_PORT_MASK    0x70

#define    RTL8367D_REG_FLOWCTRL_CTRL0    0x121d
#define    RTL8367D_DROP_ALL_THRESHOLD_OFFSET    5
#define    RTL8367D_DROP_ALL_THRESHOLD_MASK    0xFFE0
#define    RTL8367D_ITFSP_REG_OFFSET    0
#define    RTL8367D_ITFSP_REG_MASK    0x7

#define    RTL8367D_REG_FLOWCTRL_ALL_ON    0x121e
#define    RTL8367D_CFG_RLDPACT_OFFSET    12
#define    RTL8367D_CFG_RLDPACT_MASK    0x1000
#define    RTL8367D_FLOWCTRL_ALL_ON_THRESHOLD_OFFSET    0
#define    RTL8367D_FLOWCTRL_ALL_ON_THRESHOLD_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_SYS_ON    0x121f
#define    RTL8367D_FLOWCTRL_SYS_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_SYS_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_SYS_OFF    0x1220
#define    RTL8367D_FLOWCTRL_SYS_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_SYS_OFF_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_SHARE_ON    0x1221
#define    RTL8367D_FLOWCTRL_SHARE_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_SHARE_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_SHARE_OFF    0x1222
#define    RTL8367D_FLOWCTRL_SHARE_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_SHARE_OFF_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_FCOFF_SYS_ON    0x1223
#define    RTL8367D_FLOWCTRL_FCOFF_SYS_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_FCOFF_SYS_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_FCOFF_SYS_OFF    0x1224
#define    RTL8367D_FLOWCTRL_FCOFF_SYS_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_FCOFF_SYS_OFF_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_FCOFF_SHARE_ON    0x1225
#define    RTL8367D_FLOWCTRL_FCOFF_SHARE_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_FCOFF_SHARE_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_FCOFF_SHARE_OFF    0x1226
#define    RTL8367D_FLOWCTRL_FCOFF_SHARE_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_FCOFF_SHARE_OFF_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT_ON    0x1227
#define    RTL8367D_FLOWCTRL_PORT_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT_OFF    0x1228
#define    RTL8367D_FLOWCTRL_PORT_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT_OFF_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT_PRIVATE_ON    0x1229
#define    RTL8367D_FLOWCTRL_PORT_PRIVATE_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT_PRIVATE_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT_PRIVATE_OFF    0x122a
#define    RTL8367D_FLOWCTRL_PORT_PRIVATE_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT_PRIVATE_OFF_MASK    0x7FF

#define    RTL8367D_REG_RRCP_CTRL0    0x122b
#define    RTL8367D_OCPDIR_EN_OFFSET    15
#define    RTL8367D_OCPDIR_EN_MASK    0x8000
#define    RTL8367D_COL_SEL_OFFSET    14
#define    RTL8367D_COL_SEL_MASK    0x4000
#define    RTL8367D_CRS_SEL_OFFSET    13
#define    RTL8367D_CRS_SEL_MASK    0x2000

#define    RTL8367D_REG_FLOWCTRL_FCOFF_PORT_ON    0x122f
#define    RTL8367D_FLOWCTRL_FCOFF_PORT_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_FCOFF_PORT_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_FCOFF_PORT_OFF    0x1230
#define    RTL8367D_FLOWCTRL_FCOFF_PORT_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_FCOFF_PORT_OFF_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON    0x1231
#define    RTL8367D_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF    0x1232
#define    RTL8367D_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_JUMBO_SYS_ON    0x1233
#define    RTL8367D_FLOWCTRL_JUMBO_SYS_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_JUMBO_SYS_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_JUMBO_SYS_OFF    0x1234
#define    RTL8367D_FLOWCTRL_JUMBO_SYS_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_JUMBO_SYS_OFF_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_JUMBO_SHARE_ON    0x1235
#define    RTL8367D_FLOWCTRL_JUMBO_SHARE_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_JUMBO_SHARE_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_JUMBO_SHARE_OFF    0x1236
#define    RTL8367D_FLOWCTRL_JUMBO_SHARE_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_JUMBO_SHARE_OFF_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_JUMBO_PORT_ON    0x1237
#define    RTL8367D_FLOWCTRL_JUMBO_PORT_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_JUMBO_PORT_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_JUMBO_PORT_OFF    0x1238
#define    RTL8367D_FLOWCTRL_JUMBO_PORT_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_JUMBO_PORT_OFF_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_ON    0x1239
#define    RTL8367D_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_OFFSET    0
#define    RTL8367D_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF    0x123a
#define    RTL8367D_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_OFFSET    0
#define    RTL8367D_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_JUMBO_SIZE    0x123b
#define    RTL8367D_JUMBO_MODE_OFFSET    2
#define    RTL8367D_JUMBO_MODE_MASK    0x4
#define    RTL8367D_JUMBO_SIZE_OFFSET    0
#define    RTL8367D_JUMBO_SIZE_MASK    0x3

#define    RTL8367D_REG_FLOWCTRL_TOTAL_PAGE_COUNTER    0x124c
#define    RTL8367D_FLOWCTRL_TOTAL_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_TOTAL_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PUBLIC_PAGE_COUNTER    0x124d
#define    RTL8367D_FLOWCTRL_PUBLIC_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_PUBLIC_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_TOTAL_PAGE_MAX    0x124e
#define    RTL8367D_FLOWCTRL_TOTAL_PAGE_MAX_OFFSET    0
#define    RTL8367D_FLOWCTRL_TOTAL_PAGE_MAX_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PUBLIC_PAGE_MAX    0x124f
#define    RTL8367D_FLOWCTRL_PUBLIC_PAGE_MAX_OFFSET    0
#define    RTL8367D_FLOWCTRL_PUBLIC_PAGE_MAX_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT0_PAGE_COUNTER    0x1250
#define    RTL8367D_FLOWCTRL_PORT0_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT0_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT1_PAGE_COUNTER    0x1251
#define    RTL8367D_FLOWCTRL_PORT1_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT1_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT2_PAGE_COUNTER    0x1252
#define    RTL8367D_FLOWCTRL_PORT2_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT2_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT3_PAGE_COUNTER    0x1253
#define    RTL8367D_FLOWCTRL_PORT3_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT3_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT4_PAGE_COUNTER    0x1254
#define    RTL8367D_FLOWCTRL_PORT4_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT4_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT5_PAGE_COUNTER    0x1255
#define    RTL8367D_FLOWCTRL_PORT5_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT5_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT6_PAGE_COUNTER    0x1256
#define    RTL8367D_FLOWCTRL_PORT6_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT6_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT7_PAGE_COUNTER    0x1257
#define    RTL8367D_FLOWCTRL_PORT7_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT7_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER    0x1258
#define    RTL8367D_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER    0x1259
#define    RTL8367D_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER    0x125a
#define    RTL8367D_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER    0x125b
#define    RTL8367D_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER_OFFSET    0
#define    RTL8367D_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT0_PAGE_MAX    0x1260
#define    RTL8367D_FLOWCTRL_PORT0_PAGE_MAX_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT0_PAGE_MAX_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT1_PAGE_MAX    0x1261
#define    RTL8367D_FLOWCTRL_PORT1_PAGE_MAX_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT1_PAGE_MAX_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT2_PAGE_MAX    0x1262
#define    RTL8367D_FLOWCTRL_PORT2_PAGE_MAX_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT2_PAGE_MAX_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT3_PAGE_MAX    0x1263
#define    RTL8367D_FLOWCTRL_PORT3_PAGE_MAX_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT3_PAGE_MAX_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT4_PAGE_MAX    0x1264
#define    RTL8367D_FLOWCTRL_PORT4_PAGE_MAX_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT4_PAGE_MAX_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT5_PAGE_MAX    0x1265
#define    RTL8367D_FLOWCTRL_PORT5_PAGE_MAX_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT5_PAGE_MAX_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT6_PAGE_MAX    0x1266
#define    RTL8367D_FLOWCTRL_PORT6_PAGE_MAX_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT6_PAGE_MAX_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PORT7_PAGE_MAX    0x1267
#define    RTL8367D_FLOWCTRL_PORT7_PAGE_MAX_OFFSET    0
#define    RTL8367D_FLOWCTRL_PORT7_PAGE_MAX_MASK    0x7FF

#define    RTL8367D_REG_FLOWCTRL_PAGE_COUNT_CLEAR    0x1268
#define    RTL8367D_DIS_SKIP_FP_OFFSET    1
#define    RTL8367D_DIS_SKIP_FP_MASK    0x2
#define    RTL8367D_PAGE_COUNT_CLEAR_OFFSET    0
#define    RTL8367D_PAGE_COUNT_CLEAR_MASK    0x1

#define    RTL8367D_REG_WOL_CFG    0x1270
#define    RTL8367D_WOL_EN_OFFSET    8
#define    RTL8367D_WOL_EN_MASK    0x100
#define    RTL8367D_WOL_RX_MGGIC_PORTMASK_OFFSET    0
#define    RTL8367D_WOL_RX_MGGIC_PORTMASK_MASK    0xFF

#define    RTL8367D_REG_WOL_MAC0    0x1271

#define    RTL8367D_REG_WOL_MAC1    0x1272

#define    RTL8367D_REG_WOL_MAC2    0x1273

#define    RTL8367D_REG_MIB_RMON_LEN_CTRL    0x128a
#define    RTL8367D_RX_LENGTH_CTRL_OFFSET    1
#define    RTL8367D_RX_LENGTH_CTRL_MASK    0x2
#define    RTL8367D_TX_LENGTH_CTRL_OFFSET    0
#define    RTL8367D_TX_LENGTH_CTRL_MASK    0x1

#define    RTL8367D_REG_CHG_DUPLEX_CFG    0x1296
#define    RTL8367D_CFG_CHG_DUP_EN_OFFSET    7
#define    RTL8367D_CFG_CHG_DUP_EN_MASK    0x80
#define    RTL8367D_CFG_CHG_DUP_THR_OFFSET    2
#define    RTL8367D_CFG_CHG_DUP_THR_MASK    0x7C
#define    RTL8367D_CFG_CHG_DUP_CONGEST_OFFSET    1
#define    RTL8367D_CFG_CHG_DUP_CONGEST_MASK    0x2

#define    RTL8367D_REG_RX_FC_REG    0x12aa
#define    RTL8367D_RX_FC_REG_OFFSET    0
#define    RTL8367D_RX_FC_REG_MASK    0xFF

#define    RTL8367D_REG_MAX_FIFO_SIZE    0x12af
#define    RTL8367D_MAX_FIFO_SIZE_OFFSET    0
#define    RTL8367D_MAX_FIFO_SIZE_MASK    0xF

#define    RTL8367D_REG_DUMMY_REG_12_2    0x12b2

#define    RTL8367D_REG_BACK_PRESSURE_IPG    0x12be
#define    RTL8367D_FIX_PAUSE_ISSUE_OFFSET    3
#define    RTL8367D_FIX_PAUSE_ISSUE_MASK    0x8
#define    RTL8367D_REPLACE_L3_CRC_OFFSET    2
#define    RTL8367D_REPLACE_L3_CRC_MASK    0x4
#define    RTL8367D_IPG_BIT_TIME_OFFSET    0
#define    RTL8367D_IPG_BIT_TIME_MASK    0x3

#define    RTL8367D_REG_TX_ESD_LEVEL    0x12bf
#define    RTL8367D_TX_ESD_LEVEL_MODE_OFFSET    8
#define    RTL8367D_TX_ESD_LEVEL_MODE_MASK    0x100
#define    RTL8367D_LEVEL_OFFSET    0
#define    RTL8367D_LEVEL_MASK    0xFF

#define    RTL8367D_REG_MAC0_FORCE_SELECT    0x12c0
#define    RTL8367D_MAC0_FORCE_SELECT_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC0_FORCE_SELECT_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC0_FORCE_SELECT_UNUSED_OFFSET    14
#define    RTL8367D_MAC0_FORCE_SELECT_UNUSED_MASK    0x4000
#define    RTL8367D_MAC0_FORCE_SELECT_SPEED23_ABLTY_OFFSET    12
#define    RTL8367D_MAC0_FORCE_SELECT_SPEED23_ABLTY_MASK    0x3000
#define    RTL8367D_MAC0_FORCE_SELECT_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC0_FORCE_SELECT_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC0_FORCE_SELECT_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC0_FORCE_SELECT_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC0_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC0_FORCE_SELECT_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC0_FORCE_SELECT_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC0_FORCE_SELECT_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC0_FORCE_SELECT_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC0_FORCE_SELECT_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC0_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC0_FORCE_SELECT_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC0_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC0_FORCE_SELECT_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC0_FORCE_SELECT_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC0_FORCE_SELECT_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC0_FORCE_SELECT_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC0_FORCE_SELECT_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC0_FORCE_SELECT_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC0_FORCE_SELECT_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC0_FORCE_SELECT_SPEED01_ABLTY_OFFSET    0
#define    RTL8367D_MAC0_FORCE_SELECT_SPEED01_ABLTY_MASK    0x3

#define    RTL8367D_REG_MAC1_FORCE_SELECT    0x12c1
#define    RTL8367D_MAC1_FORCE_SELECT_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC1_FORCE_SELECT_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC1_FORCE_SELECT_UNUSED_OFFSET    14
#define    RTL8367D_MAC1_FORCE_SELECT_UNUSED_MASK    0x4000
#define    RTL8367D_MAC1_FORCE_SELECT_SPEED23_ABLTY_OFFSET    12
#define    RTL8367D_MAC1_FORCE_SELECT_SPEED23_ABLTY_MASK    0x3000
#define    RTL8367D_MAC1_FORCE_SELECT_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC1_FORCE_SELECT_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC1_FORCE_SELECT_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC1_FORCE_SELECT_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC1_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC1_FORCE_SELECT_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC1_FORCE_SELECT_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC1_FORCE_SELECT_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC1_FORCE_SELECT_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC1_FORCE_SELECT_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC1_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC1_FORCE_SELECT_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC1_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC1_FORCE_SELECT_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC1_FORCE_SELECT_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC1_FORCE_SELECT_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC1_FORCE_SELECT_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC1_FORCE_SELECT_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC1_FORCE_SELECT_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC1_FORCE_SELECT_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC1_FORCE_SELECT_SPEED01_ABLTY_OFFSET    0
#define    RTL8367D_MAC1_FORCE_SELECT_SPEED01_ABLTY_MASK    0x3

#define    RTL8367D_REG_MAC2_FORCE_SELECT    0x12c2
#define    RTL8367D_MAC2_FORCE_SELECT_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC2_FORCE_SELECT_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC2_FORCE_SELECT_UNUSED_OFFSET    14
#define    RTL8367D_MAC2_FORCE_SELECT_UNUSED_MASK    0x4000
#define    RTL8367D_MAC2_FORCE_SELECT_SPEED23_ABLTY_OFFSET    12
#define    RTL8367D_MAC2_FORCE_SELECT_SPEED23_ABLTY_MASK    0x3000
#define    RTL8367D_MAC2_FORCE_SELECT_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC2_FORCE_SELECT_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC2_FORCE_SELECT_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC2_FORCE_SELECT_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC2_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC2_FORCE_SELECT_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC2_FORCE_SELECT_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC2_FORCE_SELECT_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC2_FORCE_SELECT_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC2_FORCE_SELECT_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC2_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC2_FORCE_SELECT_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC2_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC2_FORCE_SELECT_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC2_FORCE_SELECT_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC2_FORCE_SELECT_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC2_FORCE_SELECT_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC2_FORCE_SELECT_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC2_FORCE_SELECT_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC2_FORCE_SELECT_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC2_FORCE_SELECT_SPEED01_ABLTY_OFFSET    0
#define    RTL8367D_MAC2_FORCE_SELECT_SPEED01_ABLTY_MASK    0x3

#define    RTL8367D_REG_MAC3_FORCE_SELECT    0x12c3
#define    RTL8367D_MAC3_FORCE_SELECT_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC3_FORCE_SELECT_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC3_FORCE_SELECT_UNUSED_OFFSET    14
#define    RTL8367D_MAC3_FORCE_SELECT_UNUSED_MASK    0x4000
#define    RTL8367D_MAC3_FORCE_SELECT_SPEED23_ABLTY_OFFSET    12
#define    RTL8367D_MAC3_FORCE_SELECT_SPEED23_ABLTY_MASK    0x3000
#define    RTL8367D_MAC3_FORCE_SELECT_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC3_FORCE_SELECT_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC3_FORCE_SELECT_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC3_FORCE_SELECT_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC3_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC3_FORCE_SELECT_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC3_FORCE_SELECT_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC3_FORCE_SELECT_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC3_FORCE_SELECT_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC3_FORCE_SELECT_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC3_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC3_FORCE_SELECT_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC3_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC3_FORCE_SELECT_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC3_FORCE_SELECT_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC3_FORCE_SELECT_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC3_FORCE_SELECT_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC3_FORCE_SELECT_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC3_FORCE_SELECT_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC3_FORCE_SELECT_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC3_FORCE_SELECT_SPEED01_ABLTY_OFFSET    0
#define    RTL8367D_MAC3_FORCE_SELECT_SPEED01_ABLTY_MASK    0x3

#define    RTL8367D_REG_MAC4_FORCE_SELECT    0x12c4
#define    RTL8367D_MAC4_FORCE_SELECT_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC4_FORCE_SELECT_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC4_FORCE_SELECT_UNUSED_OFFSET    14
#define    RTL8367D_MAC4_FORCE_SELECT_UNUSED_MASK    0x4000
#define    RTL8367D_MAC4_FORCE_SELECT_SPEED23_ABLTY_OFFSET    12
#define    RTL8367D_MAC4_FORCE_SELECT_SPEED23_ABLTY_MASK    0x3000
#define    RTL8367D_MAC4_FORCE_SELECT_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC4_FORCE_SELECT_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC4_FORCE_SELECT_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC4_FORCE_SELECT_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC4_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC4_FORCE_SELECT_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC4_FORCE_SELECT_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC4_FORCE_SELECT_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC4_FORCE_SELECT_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC4_FORCE_SELECT_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC4_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC4_FORCE_SELECT_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC4_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC4_FORCE_SELECT_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC4_FORCE_SELECT_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC4_FORCE_SELECT_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC4_FORCE_SELECT_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC4_FORCE_SELECT_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC4_FORCE_SELECT_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC4_FORCE_SELECT_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC4_FORCE_SELECT_SPEED01_ABLTY_OFFSET    0
#define    RTL8367D_MAC4_FORCE_SELECT_SPEED01_ABLTY_MASK    0x3

#define    RTL8367D_REG_MAC5_FORCE_SELECT    0x12c5
#define    RTL8367D_MAC5_FORCE_SELECT_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC5_FORCE_SELECT_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC5_FORCE_SELECT_UNUSED_OFFSET    14
#define    RTL8367D_MAC5_FORCE_SELECT_UNUSED_MASK    0x4000
#define    RTL8367D_MAC5_FORCE_SELECT_SPEED23_ABLTY_OFFSET    12
#define    RTL8367D_MAC5_FORCE_SELECT_SPEED23_ABLTY_MASK    0x3000
#define    RTL8367D_MAC5_FORCE_SELECT_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC5_FORCE_SELECT_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC5_FORCE_SELECT_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC5_FORCE_SELECT_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC5_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC5_FORCE_SELECT_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC5_FORCE_SELECT_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC5_FORCE_SELECT_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC5_FORCE_SELECT_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC5_FORCE_SELECT_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC5_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC5_FORCE_SELECT_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC5_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC5_FORCE_SELECT_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC5_FORCE_SELECT_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC5_FORCE_SELECT_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC5_FORCE_SELECT_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC5_FORCE_SELECT_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC5_FORCE_SELECT_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC5_FORCE_SELECT_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC5_FORCE_SELECT_SPEED01_ABLTY_OFFSET    0
#define    RTL8367D_MAC5_FORCE_SELECT_SPEED01_ABLTY_MASK    0x3

#define    RTL8367D_REG_MAC6_FORCE_SELECT    0x12c6
#define    RTL8367D_MAC6_FORCE_SELECT_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC6_FORCE_SELECT_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC6_FORCE_SELECT_UNUSED_OFFSET    14
#define    RTL8367D_MAC6_FORCE_SELECT_UNUSED_MASK    0x4000
#define    RTL8367D_MAC6_FORCE_SELECT_SPEED23_ABLTY_OFFSET    12
#define    RTL8367D_MAC6_FORCE_SELECT_SPEED23_ABLTY_MASK    0x3000
#define    RTL8367D_MAC6_FORCE_SELECT_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC6_FORCE_SELECT_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC6_FORCE_SELECT_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC6_FORCE_SELECT_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC6_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC6_FORCE_SELECT_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC6_FORCE_SELECT_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC6_FORCE_SELECT_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC6_FORCE_SELECT_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC6_FORCE_SELECT_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC6_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC6_FORCE_SELECT_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC6_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC6_FORCE_SELECT_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC6_FORCE_SELECT_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC6_FORCE_SELECT_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC6_FORCE_SELECT_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC6_FORCE_SELECT_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC6_FORCE_SELECT_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC6_FORCE_SELECT_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC6_FORCE_SELECT_SPEED01_ABLTY_OFFSET    0
#define    RTL8367D_MAC6_FORCE_SELECT_SPEED01_ABLTY_MASK    0x3

#define    RTL8367D_REG_MAC7_FORCE_SELECT    0x12c7
#define    RTL8367D_MAC7_FORCE_SELECT_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC7_FORCE_SELECT_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC7_FORCE_SELECT_UNUSED_OFFSET    14
#define    RTL8367D_MAC7_FORCE_SELECT_UNUSED_MASK    0x4000
#define    RTL8367D_MAC7_FORCE_SELECT_SPEED23_ABLTY_OFFSET    12
#define    RTL8367D_MAC7_FORCE_SELECT_SPEED23_ABLTY_MASK    0x3000
#define    RTL8367D_MAC7_FORCE_SELECT_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC7_FORCE_SELECT_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC7_FORCE_SELECT_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC7_FORCE_SELECT_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC7_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC7_FORCE_SELECT_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC7_FORCE_SELECT_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC7_FORCE_SELECT_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC7_FORCE_SELECT_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC7_FORCE_SELECT_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC7_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC7_FORCE_SELECT_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC7_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC7_FORCE_SELECT_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC7_FORCE_SELECT_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC7_FORCE_SELECT_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC7_FORCE_SELECT_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC7_FORCE_SELECT_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC7_FORCE_SELECT_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC7_FORCE_SELECT_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC7_FORCE_SELECT_SPEED01_ABLTY_OFFSET    0
#define    RTL8367D_MAC7_FORCE_SELECT_SPEED01_ABLTY_MASK    0x3

#define    RTL8367D_REG_MAC0_FORCE_SELECT_EN    0x12c8
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC0_FORCE_SELECT_EN_UNUSED_OFFSET    14
#define    RTL8367D_MAC0_FORCE_SELECT_EN_UNUSED_MASK    0x4000
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET    13
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK    0x2000
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET    12
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK    0x1000
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET    1
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK    0x2
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET    0
#define    RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK    0x1

#define    RTL8367D_REG_MAC1_FORCE_SELECT_EN    0x12c9
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC1_FORCE_SELECT_EN_UNUSED_OFFSET    14
#define    RTL8367D_MAC1_FORCE_SELECT_EN_UNUSED_MASK    0x4000
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET    13
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK    0x2000
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET    12
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK    0x1000
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET    1
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK    0x2
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET    0
#define    RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK    0x1

#define    RTL8367D_REG_MAC2_FORCE_SELECT_EN    0x12ca
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC2_FORCE_SELECT_EN_UNUSED_OFFSET    14
#define    RTL8367D_MAC2_FORCE_SELECT_EN_UNUSED_MASK    0x4000
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET    13
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK    0x2000
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET    12
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK    0x1000
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET    1
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK    0x2
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET    0
#define    RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK    0x1

#define    RTL8367D_REG_MAC3_FORCE_SELECT_EN    0x12cb
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC3_FORCE_SELECT_EN_UNUSED_OFFSET    14
#define    RTL8367D_MAC3_FORCE_SELECT_EN_UNUSED_MASK    0x4000
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET    13
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK    0x2000
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET    12
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK    0x1000
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET    1
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK    0x2
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET    0
#define    RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK    0x1

#define    RTL8367D_REG_MAC4_FORCE_SELECT_EN    0x12cc
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC4_FORCE_SELECT_EN_UNUSED_OFFSET    14
#define    RTL8367D_MAC4_FORCE_SELECT_EN_UNUSED_MASK    0x4000
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET    13
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK    0x2000
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET    12
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK    0x1000
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET    1
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK    0x2
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET    0
#define    RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK    0x1

#define    RTL8367D_REG_MAC5_FORCE_SELECT_EN    0x12cd
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC5_FORCE_SELECT_EN_UNUSED_OFFSET    14
#define    RTL8367D_MAC5_FORCE_SELECT_EN_UNUSED_MASK    0x4000
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET    13
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK    0x2000
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET    12
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK    0x1000
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET    1
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK    0x2
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET    0
#define    RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK    0x1

#define    RTL8367D_REG_MAC6_FORCE_SELECT_EN    0x12ce
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC6_FORCE_SELECT_EN_UNUSED_OFFSET    14
#define    RTL8367D_MAC6_FORCE_SELECT_EN_UNUSED_MASK    0x4000
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET    13
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK    0x2000
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET    12
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK    0x1000
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET    1
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK    0x2
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET    0
#define    RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK    0x1

#define    RTL8367D_REG_MAC7_FORCE_SELECT_EN    0x12cf
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET    15
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK    0x8000
#define    RTL8367D_MAC7_FORCE_SELECT_EN_UNUSED_OFFSET    14
#define    RTL8367D_MAC7_FORCE_SELECT_EN_UNUSED_MASK    0x4000
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET    13
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK    0x2000
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET    12
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK    0x1000
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET    11
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK    0x800
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET    10
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK    0x400
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET    9
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK    0x200
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET    8
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK    0x100
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET    7
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK    0x80
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET    6
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK    0x40
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET    5
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK    0x20
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET    4
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK    0x10
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET    3
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK    0x8
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET    2
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK    0x4
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET    1
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK    0x2
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET    0
#define    RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK    0x1

#define    RTL8367D_REG_PORT0_STATUS    0x12d0
#define    RTL8367D_PORT0_STATUS_EN_EEE_LPI_OFFSET    15
#define    RTL8367D_PORT0_STATUS_EN_EEE_LPI_MASK    0x8000
#define    RTL8367D_PORT0_STATUS_UNUSED_OFFSET    14
#define    RTL8367D_PORT0_STATUS_UNUSED_MASK    0x4000
#define    RTL8367D_PORT0_STATUS_LINK_SPEED_3_OFFSET    13
#define    RTL8367D_PORT0_STATUS_LINK_SPEED_3_MASK    0x2000
#define    RTL8367D_PORT0_STATUS_LINK_SPEED_2_OFFSET    12
#define    RTL8367D_PORT0_STATUS_LINK_SPEED_2_MASK    0x1000
#define    RTL8367D_PORT0_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8367D_PORT0_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8367D_PORT0_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8367D_PORT0_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8367D_PORT0_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8367D_PORT0_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8367D_PORT0_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8367D_PORT0_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8367D_PORT0_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8367D_PORT0_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8367D_PORT0_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8367D_PORT0_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8367D_PORT0_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8367D_PORT0_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8367D_PORT0_STATUS_LINK_STATE_OFFSET    4
#define    RTL8367D_PORT0_STATUS_LINK_STATE_MASK    0x10
#define    RTL8367D_PORT0_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8367D_PORT0_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8367D_PORT0_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8367D_PORT0_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8367D_REG_PORT1_STATUS    0x12d1
#define    RTL8367D_PORT1_STATUS_EN_EEE_LPI_OFFSET    15
#define    RTL8367D_PORT1_STATUS_EN_EEE_LPI_MASK    0x8000
#define    RTL8367D_PORT1_STATUS_UNUSED_OFFSET    14
#define    RTL8367D_PORT1_STATUS_UNUSED_MASK    0x4000
#define    RTL8367D_PORT1_STATUS_LINK_SPEED_3_OFFSET    13
#define    RTL8367D_PORT1_STATUS_LINK_SPEED_3_MASK    0x2000
#define    RTL8367D_PORT1_STATUS_LINK_SPEED_2_OFFSET    12
#define    RTL8367D_PORT1_STATUS_LINK_SPEED_2_MASK    0x1000
#define    RTL8367D_PORT1_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8367D_PORT1_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8367D_PORT1_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8367D_PORT1_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8367D_PORT1_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8367D_PORT1_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8367D_PORT1_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8367D_PORT1_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8367D_PORT1_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8367D_PORT1_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8367D_PORT1_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8367D_PORT1_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8367D_PORT1_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8367D_PORT1_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8367D_PORT1_STATUS_LINK_STATE_OFFSET    4
#define    RTL8367D_PORT1_STATUS_LINK_STATE_MASK    0x10
#define    RTL8367D_PORT1_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8367D_PORT1_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8367D_PORT1_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8367D_PORT1_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8367D_REG_PORT2_STATUS    0x12d2
#define    RTL8367D_PORT2_STATUS_EN_EEE_LPI_OFFSET    15
#define    RTL8367D_PORT2_STATUS_EN_EEE_LPI_MASK    0x8000
#define    RTL8367D_PORT2_STATUS_UNUSED_OFFSET    14
#define    RTL8367D_PORT2_STATUS_UNUSED_MASK    0x4000
#define    RTL8367D_PORT2_STATUS_LINK_SPEED_3_OFFSET    13
#define    RTL8367D_PORT2_STATUS_LINK_SPEED_3_MASK    0x2000
#define    RTL8367D_PORT2_STATUS_LINK_SPEED_2_OFFSET    12
#define    RTL8367D_PORT2_STATUS_LINK_SPEED_2_MASK    0x1000
#define    RTL8367D_PORT2_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8367D_PORT2_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8367D_PORT2_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8367D_PORT2_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8367D_PORT2_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8367D_PORT2_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8367D_PORT2_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8367D_PORT2_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8367D_PORT2_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8367D_PORT2_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8367D_PORT2_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8367D_PORT2_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8367D_PORT2_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8367D_PORT2_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8367D_PORT2_STATUS_LINK_STATE_OFFSET    4
#define    RTL8367D_PORT2_STATUS_LINK_STATE_MASK    0x10
#define    RTL8367D_PORT2_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8367D_PORT2_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8367D_PORT2_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8367D_PORT2_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8367D_REG_PORT3_STATUS    0x12d3
#define    RTL8367D_PORT3_STATUS_EN_EEE_LPI_OFFSET    15
#define    RTL8367D_PORT3_STATUS_EN_EEE_LPI_MASK    0x8000
#define    RTL8367D_PORT3_STATUS_UNUSED_OFFSET    14
#define    RTL8367D_PORT3_STATUS_UNUSED_MASK    0x4000
#define    RTL8367D_PORT3_STATUS_LINK_SPEED_3_OFFSET    13
#define    RTL8367D_PORT3_STATUS_LINK_SPEED_3_MASK    0x2000
#define    RTL8367D_PORT3_STATUS_LINK_SPEED_2_OFFSET    12
#define    RTL8367D_PORT3_STATUS_LINK_SPEED_2_MASK    0x1000
#define    RTL8367D_PORT3_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8367D_PORT3_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8367D_PORT3_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8367D_PORT3_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8367D_PORT3_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8367D_PORT3_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8367D_PORT3_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8367D_PORT3_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8367D_PORT3_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8367D_PORT3_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8367D_PORT3_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8367D_PORT3_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8367D_PORT3_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8367D_PORT3_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8367D_PORT3_STATUS_LINK_STATE_OFFSET    4
#define    RTL8367D_PORT3_STATUS_LINK_STATE_MASK    0x10
#define    RTL8367D_PORT3_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8367D_PORT3_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8367D_PORT3_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8367D_PORT3_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8367D_REG_PORT4_STATUS    0x12d4
#define    RTL8367D_PORT4_STATUS_EN_EEE_LPI_OFFSET    15
#define    RTL8367D_PORT4_STATUS_EN_EEE_LPI_MASK    0x8000
#define    RTL8367D_PORT4_STATUS_UNUSED_OFFSET    14
#define    RTL8367D_PORT4_STATUS_UNUSED_MASK    0x4000
#define    RTL8367D_PORT4_STATUS_LINK_SPEED_3_OFFSET    13
#define    RTL8367D_PORT4_STATUS_LINK_SPEED_3_MASK    0x2000
#define    RTL8367D_PORT4_STATUS_LINK_SPEED_2_OFFSET    12
#define    RTL8367D_PORT4_STATUS_LINK_SPEED_2_MASK    0x1000
#define    RTL8367D_PORT4_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8367D_PORT4_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8367D_PORT4_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8367D_PORT4_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8367D_PORT4_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8367D_PORT4_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8367D_PORT4_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8367D_PORT4_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8367D_PORT4_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8367D_PORT4_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8367D_PORT4_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8367D_PORT4_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8367D_PORT4_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8367D_PORT4_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8367D_PORT4_STATUS_LINK_STATE_OFFSET    4
#define    RTL8367D_PORT4_STATUS_LINK_STATE_MASK    0x10
#define    RTL8367D_PORT4_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8367D_PORT4_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8367D_PORT4_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8367D_PORT4_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8367D_REG_PORT5_STATUS    0x12d5
#define    RTL8367D_PORT5_STATUS_EN_EEE_LPI_OFFSET    15
#define    RTL8367D_PORT5_STATUS_EN_EEE_LPI_MASK    0x8000
#define    RTL8367D_PORT5_STATUS_UNUSED_OFFSET    14
#define    RTL8367D_PORT5_STATUS_UNUSED_MASK    0x4000
#define    RTL8367D_PORT5_STATUS_LINK_SPEED_3_OFFSET    13
#define    RTL8367D_PORT5_STATUS_LINK_SPEED_3_MASK    0x2000
#define    RTL8367D_PORT5_STATUS_LINK_SPEED_2_OFFSET    12
#define    RTL8367D_PORT5_STATUS_LINK_SPEED_2_MASK    0x1000
#define    RTL8367D_PORT5_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8367D_PORT5_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8367D_PORT5_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8367D_PORT5_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8367D_PORT5_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8367D_PORT5_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8367D_PORT5_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8367D_PORT5_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8367D_PORT5_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8367D_PORT5_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8367D_PORT5_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8367D_PORT5_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8367D_PORT5_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8367D_PORT5_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8367D_PORT5_STATUS_LINK_STATE_OFFSET    4
#define    RTL8367D_PORT5_STATUS_LINK_STATE_MASK    0x10
#define    RTL8367D_PORT5_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8367D_PORT5_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8367D_PORT5_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8367D_PORT5_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8367D_REG_PORT6_STATUS    0x12d6
#define    RTL8367D_PORT6_STATUS_EN_EEE_LPI_OFFSET    15
#define    RTL8367D_PORT6_STATUS_EN_EEE_LPI_MASK    0x8000
#define    RTL8367D_PORT6_STATUS_UNUSED_OFFSET    14
#define    RTL8367D_PORT6_STATUS_UNUSED_MASK    0x4000
#define    RTL8367D_PORT6_STATUS_LINK_SPEED_3_OFFSET    13
#define    RTL8367D_PORT6_STATUS_LINK_SPEED_3_MASK    0x2000
#define    RTL8367D_PORT6_STATUS_LINK_SPEED_2_OFFSET    12
#define    RTL8367D_PORT6_STATUS_LINK_SPEED_2_MASK    0x1000
#define    RTL8367D_PORT6_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8367D_PORT6_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8367D_PORT6_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8367D_PORT6_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8367D_PORT6_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8367D_PORT6_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8367D_PORT6_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8367D_PORT6_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8367D_PORT6_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8367D_PORT6_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8367D_PORT6_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8367D_PORT6_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8367D_PORT6_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8367D_PORT6_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8367D_PORT6_STATUS_LINK_STATE_OFFSET    4
#define    RTL8367D_PORT6_STATUS_LINK_STATE_MASK    0x10
#define    RTL8367D_PORT6_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8367D_PORT6_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8367D_PORT6_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8367D_PORT6_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8367D_REG_PORT7_STATUS    0x12d7
#define    RTL8367D_PORT7_STATUS_EN_EEE_LPI_OFFSET    15
#define    RTL8367D_PORT7_STATUS_EN_EEE_LPI_MASK    0x8000
#define    RTL8367D_PORT7_STATUS_UNUSED_OFFSET    14
#define    RTL8367D_PORT7_STATUS_UNUSED_MASK    0x4000
#define    RTL8367D_PORT7_STATUS_LINK_SPEED_3_OFFSET    13
#define    RTL8367D_PORT7_STATUS_LINK_SPEED_3_MASK    0x2000
#define    RTL8367D_PORT7_STATUS_LINK_SPEED_2_OFFSET    12
#define    RTL8367D_PORT7_STATUS_LINK_SPEED_2_MASK    0x1000
#define    RTL8367D_PORT7_STATUS_EN_1000_LPI_OFFSET    11
#define    RTL8367D_PORT7_STATUS_EN_1000_LPI_MASK    0x800
#define    RTL8367D_PORT7_STATUS_EN_100_LPI_OFFSET    10
#define    RTL8367D_PORT7_STATUS_EN_100_LPI_MASK    0x400
#define    RTL8367D_PORT7_STATUS_NWAY_FAULT_OFFSET    9
#define    RTL8367D_PORT7_STATUS_NWAY_FAULT_MASK    0x200
#define    RTL8367D_PORT7_STATUS_LINK_ON_MASTER_OFFSET    8
#define    RTL8367D_PORT7_STATUS_LINK_ON_MASTER_MASK    0x100
#define    RTL8367D_PORT7_STATUS_NWAY_CAP_OFFSET    7
#define    RTL8367D_PORT7_STATUS_NWAY_CAP_MASK    0x80
#define    RTL8367D_PORT7_STATUS_TX_FLOWCTRL_CAP_OFFSET    6
#define    RTL8367D_PORT7_STATUS_TX_FLOWCTRL_CAP_MASK    0x40
#define    RTL8367D_PORT7_STATUS_RX_FLOWCTRL_CAP_OFFSET    5
#define    RTL8367D_PORT7_STATUS_RX_FLOWCTRL_CAP_MASK    0x20
#define    RTL8367D_PORT7_STATUS_LINK_STATE_OFFSET    4
#define    RTL8367D_PORT7_STATUS_LINK_STATE_MASK    0x10
#define    RTL8367D_PORT7_STATUS_FULL_DUPLUX_CAP_OFFSET    2
#define    RTL8367D_PORT7_STATUS_FULL_DUPLUX_CAP_MASK    0x4
#define    RTL8367D_PORT7_STATUS_LINK_SPEED_OFFSET    0
#define    RTL8367D_PORT7_STATUS_LINK_SPEED_MASK    0x3

#define    RTL8367D_REG_FIELD_SELECTOR0    0x12e7
#define    RTL8367D_FIELD_SELECTOR0_FORMAT_OFFSET    8
#define    RTL8367D_FIELD_SELECTOR0_FORMAT_MASK    0x700
#define    RTL8367D_FIELD_SELECTOR0_OFFSET_OFFSET    0
#define    RTL8367D_FIELD_SELECTOR0_OFFSET_MASK    0xFF

#define    RTL8367D_REG_FIELD_SELECTOR1    0x12e8
#define    RTL8367D_FIELD_SELECTOR1_FORMAT_OFFSET    8
#define    RTL8367D_FIELD_SELECTOR1_FORMAT_MASK    0x700
#define    RTL8367D_FIELD_SELECTOR1_OFFSET_OFFSET    0
#define    RTL8367D_FIELD_SELECTOR1_OFFSET_MASK    0xFF

#define    RTL8367D_REG_FIELD_SELECTOR2    0x12e9
#define    RTL8367D_FIELD_SELECTOR2_FORMAT_OFFSET    8
#define    RTL8367D_FIELD_SELECTOR2_FORMAT_MASK    0x700
#define    RTL8367D_FIELD_SELECTOR2_OFFSET_OFFSET    0
#define    RTL8367D_FIELD_SELECTOR2_OFFSET_MASK    0xFF

#define    RTL8367D_REG_FIELD_SELECTOR3    0x12ea
#define    RTL8367D_FIELD_SELECTOR3_FORMAT_OFFSET    8
#define    RTL8367D_FIELD_SELECTOR3_FORMAT_MASK    0x700
#define    RTL8367D_FIELD_SELECTOR3_OFFSET_OFFSET    0
#define    RTL8367D_FIELD_SELECTOR3_OFFSET_MASK    0xFF

#define    RTL8367D_REG_FIELD_SELECTOR4    0x12eb
#define    RTL8367D_FIELD_SELECTOR4_FORMAT_OFFSET    8
#define    RTL8367D_FIELD_SELECTOR4_FORMAT_MASK    0x700
#define    RTL8367D_FIELD_SELECTOR4_OFFSET_OFFSET    0
#define    RTL8367D_FIELD_SELECTOR4_OFFSET_MASK    0xFF

#define    RTL8367D_REG_FIELD_SELECTOR5    0x12ec
#define    RTL8367D_FIELD_SELECTOR5_FORMAT_OFFSET    8
#define    RTL8367D_FIELD_SELECTOR5_FORMAT_MASK    0x700
#define    RTL8367D_FIELD_SELECTOR5_OFFSET_OFFSET    0
#define    RTL8367D_FIELD_SELECTOR5_OFFSET_MASK    0xFF

#define    RTL8367D_REG_FIELD_SELECTOR6    0x12ed
#define    RTL8367D_FIELD_SELECTOR6_FORMAT_OFFSET    8
#define    RTL8367D_FIELD_SELECTOR6_FORMAT_MASK    0x700
#define    RTL8367D_FIELD_SELECTOR6_OFFSET_OFFSET    0
#define    RTL8367D_FIELD_SELECTOR6_OFFSET_MASK    0xFF

#define    RTL8367D_REG_FIELD_SELECTOR7    0x12ee
#define    RTL8367D_FIELD_SELECTOR7_FORMAT_OFFSET    8
#define    RTL8367D_FIELD_SELECTOR7_FORMAT_MASK    0x700
#define    RTL8367D_FIELD_SELECTOR7_OFFSET_OFFSET    0
#define    RTL8367D_FIELD_SELECTOR7_OFFSET_MASK    0xFF

#define    RTL8367D_REG_HAS_BISD_CTRL0    0x12ef
#define    RTL8367D_HSARAM_FRCTL_OFFSET    13
#define    RTL8367D_HSARAM_FRCTL_MASK    0x2000
#define    RTL8367D_HSARAM_TGL_OFFSET    12
#define    RTL8367D_HSARAM_TGL_MASK    0x1000
#define    RTL8367D_HSARAM_WR_OFFSET    11
#define    RTL8367D_HSARAM_WR_MASK    0x800
#define    RTL8367D_HSARAM_ADR_OFFSET    0
#define    RTL8367D_HSARAM_ADR_MASK    0x7FF

#define    RTL8367D_REG_HAS_BISD_CTRL1    0x12f0

#define    RTL8367D_REG_HAS_BISD_CTRL2    0x12f1

#define    RTL8367D_REG_HAS_BISD_CTRL3    0x12f2
#define    RTL8367D_HSARAM_BISD_EN_OFFSET    6
#define    RTL8367D_HSARAM_BISD_EN_MASK    0x40
#define    RTL8367D_HSARAM_CONS_VAL_OFFSET    5
#define    RTL8367D_HSARAM_CONS_VAL_MASK    0x20
#define    RTL8367D_HSARAM_CONS_ACS_OFFSET    4
#define    RTL8367D_HSARAM_CONS_ACS_MASK    0x10
#define    RTL8367D_HSARAM_SEL16BNK_OFFSET    0
#define    RTL8367D_HSARAM_SEL16BNK_MASK    0xF

#define    RTL8367D_REG_HAS_BISD_CTRL4    0x12f3

#define    RTL8367D_REG_PB_BISD_CTRL0    0x12f4
#define    RTL8367D_PB_FRCTL_OFFSET    15
#define    RTL8367D_PB_FRCTL_MASK    0x8000
#define    RTL8367D_PB_TGL_OFFSET    14
#define    RTL8367D_PB_TGL_MASK    0x4000
#define    RTL8367D_PB_WR_OFFSET    13
#define    RTL8367D_PB_WR_MASK    0x2000
#define    RTL8367D_PB_ADR_OFFSET    0
#define    RTL8367D_PB_ADR_MASK    0x1FFF

#define    RTL8367D_REG_PB_BISD_CTRL1    0x12f5

#define    RTL8367D_REG_PB_BISD_CTRL2    0x12f6

#define    RTL8367D_REG_PB_BISD_CTRL3    0x12f7
#define    RTL8367D_PB_BISD_EN_OFFSET    6
#define    RTL8367D_PB_BISD_EN_MASK    0x40
#define    RTL8367D_PB_CONS_VAL_OFFSET    5
#define    RTL8367D_PB_CONS_VAL_MASK    0x20
#define    RTL8367D_PB_CONS_ACS_OFFSET    4
#define    RTL8367D_PB_CONS_ACS_MASK    0x10
#define    RTL8367D_PB_SEL16BNK_OFFSET    0
#define    RTL8367D_PB_SEL16BNK_MASK    0xF

#define    RTL8367D_REG_PB_BISD_CTRL4    0x12f8

#define    RTL8367D_REG_MIRROR_SRC_PMSK    0x12fb
#define    RTL8367D_MIRROR_RX_PMSK_OFFSET    8
#define    RTL8367D_MIRROR_RX_PMSK_MASK    0xFF00
#define    RTL8367D_MIRROR_TX_PMSK_OFFSET    0
#define    RTL8367D_MIRROR_TX_PMSK_MASK    0xFF

#define    RTL8367D_REG_HWPKT_GEN_MISC    0x12ff
#define    RTL8367D_PKT_GEN_SUSPEND_OFFSET    8
#define    RTL8367D_PKT_GEN_SUSPEND_MASK    0xFF00
#define    RTL8367D_PKT_GEN_STATUS_OFFSET    0
#define    RTL8367D_PKT_GEN_STATUS_MASK    0xFF

/* (16'h1300)chip_reg */

#define    RTL8367D_REG_CHIP_NUMBER    0x1300

#define    RTL8367D_REG_CHIP_VER    0x1301
#define    RTL8367D_VERID_OFFSET    12
#define    RTL8367D_VERID_MASK    0xF000
#define    RTL8367D_MCID_OFFSET    8
#define    RTL8367D_MCID_MASK    0xF00
#define    RTL8367D_MODEL_ID_OFFSET    4
#define    RTL8367D_MODEL_ID_MASK    0xF0
#define    RTL8367D_AFE_VERSION_OFFSET    0
#define    RTL8367D_AFE_VERSION_MASK    0x1

#define    RTL8367D_REG_CFG_SLR_SMT    0x1302
#define    RTL8367D_SMT_SMI1_EN_OFFSET    4
#define    RTL8367D_SMT_SMI1_EN_MASK    0x10
#define    RTL8367D_SMT_EXT1_EN_OFFSET    3
#define    RTL8367D_SMT_EXT1_EN_MASK    0x8
#define    RTL8367D_SMT_NRST_EN_OFFSET    2
#define    RTL8367D_SMT_NRST_EN_MASK    0x4
#define    RTL8367D_SLR_EXT1CK_OFFSET    1
#define    RTL8367D_SLR_EXT1CK_MASK    0x2
#define    RTL8367D_SLR_LED_OFFSET    0
#define    RTL8367D_SLR_LED_MASK    0x1

#define    RTL8367D_REG_CHIP_DEBUG0    0x1303
#define    RTL8367D_DRI_SPI_OFFSET    14
#define    RTL8367D_DRI_SPI_MASK    0x4000
#define    RTL8367D_DRI_OFFSET    13
#define    RTL8367D_DRI_MASK    0x2000
#define    RTL8367D_SLR_SPI_OFFSET    12
#define    RTL8367D_SLR_SPI_MASK    0x1000
#define    RTL8367D_SLR_OFFSET    11
#define    RTL8367D_SLR_MASK    0x800
#define    RTL8367D_SEL33_EXT2_OFFSET    10
#define    RTL8367D_SEL33_EXT2_MASK    0x400
#define    RTL8367D_SEL33_EXT1_OFFSET    9
#define    RTL8367D_SEL33_EXT1_MASK    0x200
#define    RTL8367D_SEL33_EXT0_OFFSET    8
#define    RTL8367D_SEL33_EXT0_MASK    0x100
#define    RTL8367D_DRI_OTHER_OFFSET    7
#define    RTL8367D_DRI_OTHER_MASK    0x80
#define    RTL8367D_DRI_EXT1_RG_OFFSET    6
#define    RTL8367D_DRI_EXT1_RG_MASK    0x40
#define    RTL8367D_DRI_EXT0_RG_OFFSET    5
#define    RTL8367D_DRI_EXT0_RG_MASK    0x20
#define    RTL8367D_DRI_EXT1_OFFSET    4
#define    RTL8367D_DRI_EXT1_MASK    0x10
#define    RTL8367D_DRI_EXT0_OFFSET    3
#define    RTL8367D_DRI_EXT0_MASK    0x8
#define    RTL8367D_SLR_OTHER_OFFSET    2
#define    RTL8367D_SLR_OTHER_MASK    0x4
#define    RTL8367D_SLR_EXT1_OFFSET    1
#define    RTL8367D_SLR_EXT1_MASK    0x2
#define    RTL8367D_SLR_EXt0_OFFSET    0
#define    RTL8367D_SLR_EXt0_MASK    0x1

#define    RTL8367D_REG_CHIP_DEBUG1    0x1304
#define    RTL8367D_RG1_DN_OFFSET    12
#define    RTL8367D_RG1_DN_MASK    0x7000
#define    RTL8367D_RG1_DP_OFFSET    8
#define    RTL8367D_RG1_DP_MASK    0x700
#define    RTL8367D_RG0_DN_OFFSET    4
#define    RTL8367D_RG0_DN_MASK    0x70
#define    RTL8367D_RG0_DP_OFFSET    0
#define    RTL8367D_RG0_DP_MASK    0x7

#define    RTL8367D_REG_DIGITAL_INTERFACE_SELECT    0x1305
#define    RTL8367D_ORG_COL_OFFSET    15
#define    RTL8367D_ORG_COL_MASK    0x8000
#define    RTL8367D_ORG_CRS_OFFSET    14
#define    RTL8367D_ORG_CRS_MASK    0x4000
#define    RTL8367D_SKIP_MII_1_RXER_OFFSET    13
#define    RTL8367D_SKIP_MII_1_RXER_MASK    0x2000
#define    RTL8367D_SKIP_MII_0_RXER_OFFSET    12
#define    RTL8367D_SKIP_MII_0_RXER_MASK    0x1000
#define    RTL8367D_SELECT_GMII_1_OFFSET    4
#define    RTL8367D_SELECT_GMII_1_MASK    0xF0
#define    RTL8367D_SELECT_GMII_0_OFFSET    0
#define    RTL8367D_SELECT_GMII_0_MASK    0xF

#define    RTL8367D_REG_EXT0_RGMXF    0x1306
#define    RTL8367D_EXT0_RGTX_INV_OFFSET    6
#define    RTL8367D_EXT0_RGTX_INV_MASK    0x40
#define    RTL8367D_EXT0_RGRX_INV_OFFSET    5
#define    RTL8367D_EXT0_RGRX_INV_MASK    0x20
#define    RTL8367D_EXT0_RGMXF_OFFSET    0
#define    RTL8367D_EXT0_RGMXF_MASK    0x1F

#define    RTL8367D_REG_EXT1_RGMXF    0x1307
#define    RTL8367D_EXT1_RGTX_INV_OFFSET    6
#define    RTL8367D_EXT1_RGTX_INV_MASK    0x40
#define    RTL8367D_EXT1_RGRX_INV_OFFSET    5
#define    RTL8367D_EXT1_RGRX_INV_MASK    0x20
#define    RTL8367D_EXT1_RGMXF_OFFSET    0
#define    RTL8367D_EXT1_RGMXF_MASK    0x1F

#define    RTL8367D_REG_BISR_CTRL    0x1308
#define    RTL8367D_BISR_CTRL_OFFSET    0
#define    RTL8367D_BISR_CTRL_MASK    0x7

#define    RTL8367D_REG_I2C_CLOCK_DIV    0x130a
#define    RTL8367D_I2C_CLOCK_DIV_OFFSET    0
#define    RTL8367D_I2C_CLOCK_DIV_MASK    0x3FF

#define    RTL8367D_REG_MDX_MDC_DIV    0x130b
#define    RTL8367D_MDX_MDC_DIV_OFFSET    0
#define    RTL8367D_MDX_MDC_DIV_MASK    0x3FF

#define    RTL8367D_REG_MISCELLANEOUS_CONFIGURE0    0x130c
#define    RTL8367D_FLASH_ENABLE_OFFSET    12
#define    RTL8367D_FLASH_ENABLE_MASK    0x1000
#define    RTL8367D_EEE_ENABLE_OFFSET    11
#define    RTL8367D_EEE_ENABLE_MASK    0x800
#define    RTL8367D_NIC_ENABLE_OFFSET    10
#define    RTL8367D_NIC_ENABLE_MASK    0x400
#define    RTL8367D_FT_ENABLE_OFFSET    9
#define    RTL8367D_FT_ENABLE_MASK    0x200
#define    RTL8367D_OLT_ENABLE_OFFSET    8
#define    RTL8367D_OLT_ENABLE_MASK    0x100
#define    RTL8367D_RTCT_EN_OFFSET    7
#define    RTL8367D_RTCT_EN_MASK    0x80
#define    RTL8367D_PON_LIGHT_EN_OFFSET    6
#define    RTL8367D_PON_LIGHT_EN_MASK    0x40
#define    RTL8367D_DW8051_EN_OFFSET    5
#define    RTL8367D_DW8051_EN_MASK    0x20
#define    RTL8367D_AUTOLOAD_EN_OFFSET    4
#define    RTL8367D_AUTOLOAD_EN_MASK    0x10
#define    RTL8367D_NRESTORE_EN_OFFSET    3
#define    RTL8367D_NRESTORE_EN_MASK    0x8
#define    RTL8367D_DIS_PON_TABLE_INIT_OFFSET    2
#define    RTL8367D_DIS_PON_TABLE_INIT_MASK    0x4
#define    RTL8367D_DIS_PON_BIST_OFFSET    1
#define    RTL8367D_DIS_PON_BIST_MASK    0x2
#define    RTL8367D_EFUSE_EN_OFFSET    0
#define    RTL8367D_EFUSE_EN_MASK    0x1

#define    RTL8367D_REG_MISCELLANEOUS_CONFIGURE1    0x130d
#define    RTL8367D_GPHY_SMI_EN_OFFSET    15
#define    RTL8367D_GPHY_SMI_EN_MASK    0x8000
#define    RTL8367D_EEPROM_DEV_ADR_OFFSET    8
#define    RTL8367D_EEPROM_DEV_ADR_MASK    0x7F00
#define    RTL8367D_EEPROM_MSB_OFFSET    7
#define    RTL8367D_EEPROM_MSB_MASK    0x80
#define    RTL8367D_EEPROM_ADDRESS_16B_OFFSET    6
#define    RTL8367D_EEPROM_ADDRESS_16B_MASK    0x40
#define    RTL8367D_SPI_SLAVE_EN_OFFSET    2
#define    RTL8367D_SPI_SLAVE_EN_MASK    0x4
#define    RTL8367D_SMI_SEL_OFFSET    0
#define    RTL8367D_SMI_SEL_MASK    0x3

#define    RTL8367D_REG_PHY_AD    0x130f
#define    RTL8367D_EN_PHY_MAX_POWER_OFFSET    14
#define    RTL8367D_EN_PHY_MAX_POWER_MASK    0x4000
#define    RTL8367D_EN_PHY_SEL_DEG_OFFSET    13
#define    RTL8367D_EN_PHY_SEL_DEG_MASK    0x2000
#define    RTL8367D_EXTPHY_AD_OFFSET    8
#define    RTL8367D_EXTPHY_AD_MASK    0x1F00
#define    RTL8367D_EN_PHY_LOW_POWER_MODE_OFFSET    7
#define    RTL8367D_EN_PHY_LOW_POWER_MODE_MASK    0x80
#define    RTL8367D_EN_PHY_GREEN_OFFSET    6
#define    RTL8367D_EN_PHY_GREEN_MASK    0x40
#define    RTL8367D_PDNPHY_OFFSET    5
#define    RTL8367D_PDNPHY_MASK    0x20
#define    RTL8367D_INTPHY_AD_OFFSET    0
#define    RTL8367D_INTPHY_AD_MASK    0x1F

#define    RTL8367D_REG_CHIP_RESET    0x1322
#define    RTL8367D_GPHY_RESET_OFFSET    6
#define    RTL8367D_GPHY_RESET_MASK    0x40
#define    RTL8367D_NIC_RST_OFFSET    5
#define    RTL8367D_NIC_RST_MASK    0x20
#define    RTL8367D_DW8051_RST_OFFSET    4
#define    RTL8367D_DW8051_RST_MASK    0x10
#define    RTL8367D_SDS_RST_OFFSET    3
#define    RTL8367D_SDS_RST_MASK    0x8
#define    RTL8367D_CONFIG_RST_OFFSET    2
#define    RTL8367D_CONFIG_RST_MASK    0x4
#define    RTL8367D_SW_RST_OFFSET    1
#define    RTL8367D_SW_RST_MASK    0x2
#define    RTL8367D_CHIP_RST_OFFSET    0
#define    RTL8367D_CHIP_RST_MASK    0x1

#define    RTL8367D_REG_DIGITAL_DEBUG_0    0x1323

#define    RTL8367D_REG_DIGITAL_DEBUG_1    0x1324

#define    RTL8367D_REG_INTERNAL_PHY_MDC_DRIVER    0x1325
#define    RTL8367D_INTERNAL_PHY_MDC_DRIVER_OFFSET    0
#define    RTL8367D_INTERNAL_PHY_MDC_DRIVER_MASK    0x3FF

#define    RTL8367D_REG_LINKDOWN_TIME_CTRL    0x1326
#define    RTL8367D_LINKDOWN_TIME_CFG_OFFSET    9
#define    RTL8367D_LINKDOWN_TIME_CFG_MASK    0x7E00
#define    RTL8367D_LINKDOWN_TIME_ENABLE_OFFSET    8
#define    RTL8367D_LINKDOWN_TIME_ENABLE_MASK    0x100
#define    RTL8367D_LINKDOWN_TIME_OFFSET    0
#define    RTL8367D_LINKDOWN_TIME_MASK    0xFF

#define    RTL8367D_REG_PHYACK_TIMEOUT    0x1331

#define    RTL8367D_REG_MDXACK_TIMEOUT    0x1333

#define    RTL8367D_REG_DW8051_RDY    0x1336
#define    RTL8367D_VIAROM_WRITE_EN_OFFSET    9
#define    RTL8367D_VIAROM_WRITE_EN_MASK    0x200
#define    RTL8367D_SPIF_CK2_OFFSET    8
#define    RTL8367D_SPIF_CK2_MASK    0x100
#define    RTL8367D_EEPROM_EN_OFFSET    7
#define    RTL8367D_EEPROM_EN_MASK    0x80
#define    RTL8367D_DW8051_RATE_OFFSET    4
#define    RTL8367D_DW8051_RATE_MASK    0x70
#define    RTL8367D_IROM_MSB_OFFSET    2
#define    RTL8367D_IROM_MSB_MASK    0xC
#define    RTL8367D_ACS_IROM_ENABLE_OFFSET    1
#define    RTL8367D_ACS_IROM_ENABLE_MASK    0x2
#define    RTL8367D_DW8051_READY_OFFSET    0
#define    RTL8367D_DW8051_READY_MASK    0x1

#define    RTL8367D_REG_DIAG_MODE2    0x133d
#define    RTL8367D_DIAG_MODE2_ACTRAM_OFFSET    1
#define    RTL8367D_DIAG_MODE2_ACTRAM_MASK    0x2
#define    RTL8367D_DIAG_MODE2_BCAM_ACTION_OFFSET    0
#define    RTL8367D_DIAG_MODE2_BCAM_ACTION_MASK    0x1

#define    RTL8367D_REG_MDX_PHY_REG0    0x133e
#define    RTL8367D_PHY_BRD_MASK_OFFSET    4
#define    RTL8367D_PHY_BRD_MASK_MASK    0x1F0
#define    RTL8367D_MDX_INDACC_PAGE_OFFSET    0
#define    RTL8367D_MDX_INDACC_PAGE_MASK    0xF

#define    RTL8367D_REG_MDX_PHY_REG1    0x133f
#define    RTL8367D_PHY_BRD_MODE_OFFSET    5
#define    RTL8367D_PHY_BRD_MODE_MASK    0x20
#define    RTL8367D_BRD_PHYAD_OFFSET    0
#define    RTL8367D_BRD_PHYAD_MASK    0x1F

#define    RTL8367D_REG_DEBUG_SIGNAL_SELECT_A    0x1340

#define    RTL8367D_REG_DEBUG_SIGNAL_SELECT_B    0x1341
#define    RTL8367D_DEBUG_SEL_OFFSET    4
#define    RTL8367D_DEBUG_SEL_MASK    0x70
#define    RTL8367D_DEBUG_SHIFT_OFFSET    0
#define    RTL8367D_DEBUG_SHIFT_MASK    0xF

#define    RTL8367D_REG_DEBUG_SIGNAL_I    0x1343

#define    RTL8367D_REG_DEBUG_SIGNAL_H    0x1344

#define    RTL8367D_REG_SD_TX_IDLE_TMR    0x1349
#define    RTL8367D_SD_TX_IDLE_TMR_OFFSET    0
#define    RTL8367D_SD_TX_IDLE_TMR_MASK    0xFF

#define    RTL8367D_REG_BYPASS_ABLTY_LOCK    0x134a
#define    RTL8367D_BYPASS_PHY_OFFSET    3
#define    RTL8367D_BYPASS_PHY_MASK    0xF8
#define    RTL8367D_BYPASS_EXT_OFFSET    0
#define    RTL8367D_BYPASS_EXT_MASK    0x7

#define    RTL8367D_REG_ACL_GPIO0    0x134c
#define    RTL8367D_ACL_GPIO_15_OFFSET    15
#define    RTL8367D_ACL_GPIO_15_MASK    0x8000
#define    RTL8367D_ACL_GPIO_14_OFFSET    14
#define    RTL8367D_ACL_GPIO_14_MASK    0x4000
#define    RTL8367D_ACL_GPIO_13_OFFSET    13
#define    RTL8367D_ACL_GPIO_13_MASK    0x2000
#define    RTL8367D_ACL_GPIO_12_OFFSET    12
#define    RTL8367D_ACL_GPIO_12_MASK    0x1000
#define    RTL8367D_ACL_GPIO_11_OFFSET    11
#define    RTL8367D_ACL_GPIO_11_MASK    0x800
#define    RTL8367D_ACL_GPIO_10_OFFSET    10
#define    RTL8367D_ACL_GPIO_10_MASK    0x400
#define    RTL8367D_ACL_GPIO_9_OFFSET    9
#define    RTL8367D_ACL_GPIO_9_MASK    0x200
#define    RTL8367D_ACL_GPIO_8_OFFSET    8
#define    RTL8367D_ACL_GPIO_8_MASK    0x100
#define    RTL8367D_ACL_GPIO_7_OFFSET    7
#define    RTL8367D_ACL_GPIO_7_MASK    0x80
#define    RTL8367D_ACL_GPIO_6_OFFSET    6
#define    RTL8367D_ACL_GPIO_6_MASK    0x40
#define    RTL8367D_ACL_GPIO_5_OFFSET    5
#define    RTL8367D_ACL_GPIO_5_MASK    0x20
#define    RTL8367D_ACL_GPIO_4_OFFSET    4
#define    RTL8367D_ACL_GPIO_4_MASK    0x10
#define    RTL8367D_ACL_GPIO_3_OFFSET    3
#define    RTL8367D_ACL_GPIO_3_MASK    0x8
#define    RTL8367D_ACL_GPIO_2_OFFSET    2
#define    RTL8367D_ACL_GPIO_2_MASK    0x4
#define    RTL8367D_ACL_GPIO_1_OFFSET    1
#define    RTL8367D_ACL_GPIO_1_MASK    0x2
#define    RTL8367D_ACL_GPIO_0_OFFSET    0
#define    RTL8367D_ACL_GPIO_0_MASK    0x1

#define    RTL8367D_REG_ACL_GPIO1    0x134d
#define    RTL8367D_ACL_GPIO_31_OFFSET    15
#define    RTL8367D_ACL_GPIO_31_MASK    0x8000
#define    RTL8367D_ACL_GPIO_30_OFFSET    14
#define    RTL8367D_ACL_GPIO_30_MASK    0x4000
#define    RTL8367D_ACL_GPIO_29_OFFSET    13
#define    RTL8367D_ACL_GPIO_29_MASK    0x2000
#define    RTL8367D_ACL_GPIO_28_OFFSET    12
#define    RTL8367D_ACL_GPIO_28_MASK    0x1000
#define    RTL8367D_ACL_GPIO_27_OFFSET    11
#define    RTL8367D_ACL_GPIO_27_MASK    0x800
#define    RTL8367D_ACL_GPIO_26_OFFSET    10
#define    RTL8367D_ACL_GPIO_26_MASK    0x400
#define    RTL8367D_ACL_GPIO_25_OFFSET    9
#define    RTL8367D_ACL_GPIO_25_MASK    0x200
#define    RTL8367D_ACL_GPIO_24_OFFSET    8
#define    RTL8367D_ACL_GPIO_24_MASK    0x100
#define    RTL8367D_ACL_GPIO_23_OFFSET    7
#define    RTL8367D_ACL_GPIO_23_MASK    0x80
#define    RTL8367D_ACL_GPIO_22_OFFSET    6
#define    RTL8367D_ACL_GPIO_22_MASK    0x40
#define    RTL8367D_ACL_GPIO_21_OFFSET    5
#define    RTL8367D_ACL_GPIO_21_MASK    0x20
#define    RTL8367D_ACL_GPIO_20_OFFSET    4
#define    RTL8367D_ACL_GPIO_20_MASK    0x10
#define    RTL8367D_ACL_GPIO_19_OFFSET    3
#define    RTL8367D_ACL_GPIO_19_MASK    0x8
#define    RTL8367D_ACL_GPIO_18_OFFSET    2
#define    RTL8367D_ACL_GPIO_18_MASK    0x4
#define    RTL8367D_ACL_GPIO_17_OFFSET    1
#define    RTL8367D_ACL_GPIO_17_MASK    0x2
#define    RTL8367D_ACL_GPIO_16_OFFSET    0
#define    RTL8367D_ACL_GPIO_16_MASK    0x1

#define    RTL8367D_REG_ACL_GPIO2    0x134e
#define    RTL8367D_ACL_GPIO_47_OFFSET    15
#define    RTL8367D_ACL_GPIO_47_MASK    0x8000
#define    RTL8367D_ACL_GPIO_46_OFFSET    14
#define    RTL8367D_ACL_GPIO_46_MASK    0x4000
#define    RTL8367D_ACL_GPIO_45_OFFSET    13
#define    RTL8367D_ACL_GPIO_45_MASK    0x2000
#define    RTL8367D_ACL_GPIO_44_OFFSET    12
#define    RTL8367D_ACL_GPIO_44_MASK    0x1000
#define    RTL8367D_ACL_GPIO_43_OFFSET    11
#define    RTL8367D_ACL_GPIO_43_MASK    0x800
#define    RTL8367D_ACL_GPIO_42_OFFSET    10
#define    RTL8367D_ACL_GPIO_42_MASK    0x400
#define    RTL8367D_ACL_GPIO_41_OFFSET    9
#define    RTL8367D_ACL_GPIO_41_MASK    0x200
#define    RTL8367D_ACL_GPIO_40_OFFSET    8
#define    RTL8367D_ACL_GPIO_40_MASK    0x100
#define    RTL8367D_ACL_GPIO_39_OFFSET    7
#define    RTL8367D_ACL_GPIO_39_MASK    0x80
#define    RTL8367D_ACL_GPIO_38_OFFSET    6
#define    RTL8367D_ACL_GPIO_38_MASK    0x40
#define    RTL8367D_ACL_GPIO_37_OFFSET    5
#define    RTL8367D_ACL_GPIO_37_MASK    0x20
#define    RTL8367D_ACL_GPIO_36_OFFSET    4
#define    RTL8367D_ACL_GPIO_36_MASK    0x10
#define    RTL8367D_ACL_GPIO_35_OFFSET    3
#define    RTL8367D_ACL_GPIO_35_MASK    0x8
#define    RTL8367D_ACL_GPIO_34_OFFSET    2
#define    RTL8367D_ACL_GPIO_34_MASK    0x4
#define    RTL8367D_ACL_GPIO_33_OFFSET    1
#define    RTL8367D_ACL_GPIO_33_MASK    0x2
#define    RTL8367D_ACL_GPIO_32_OFFSET    0
#define    RTL8367D_ACL_GPIO_32_MASK    0x1

#define    RTL8367D_REG_ACL_GPIO3    0x134f
#define    RTL8367D_ACL_GPIO_61_OFFSET    13
#define    RTL8367D_ACL_GPIO_61_MASK    0x2000
#define    RTL8367D_ACL_GPIO_60_OFFSET    12
#define    RTL8367D_ACL_GPIO_60_MASK    0x1000
#define    RTL8367D_ACL_GPIO_59_OFFSET    11
#define    RTL8367D_ACL_GPIO_59_MASK    0x800
#define    RTL8367D_ACL_GPIO_58_OFFSET    10
#define    RTL8367D_ACL_GPIO_58_MASK    0x400
#define    RTL8367D_ACL_GPIO_57_OFFSET    9
#define    RTL8367D_ACL_GPIO_57_MASK    0x200
#define    RTL8367D_ACL_GPIO_56_OFFSET    8
#define    RTL8367D_ACL_GPIO_56_MASK    0x100
#define    RTL8367D_ACL_GPIO_55_OFFSET    7
#define    RTL8367D_ACL_GPIO_55_MASK    0x80
#define    RTL8367D_ACL_GPIO_54_OFFSET    6
#define    RTL8367D_ACL_GPIO_54_MASK    0x40
#define    RTL8367D_ACL_GPIO_53_OFFSET    5
#define    RTL8367D_ACL_GPIO_53_MASK    0x20
#define    RTL8367D_ACL_GPIO_52_OFFSET    4
#define    RTL8367D_ACL_GPIO_52_MASK    0x10
#define    RTL8367D_ACL_GPIO_51_OFFSET    3
#define    RTL8367D_ACL_GPIO_51_MASK    0x8
#define    RTL8367D_ACL_GPIO_50_OFFSET    2
#define    RTL8367D_ACL_GPIO_50_MASK    0x4
#define    RTL8367D_ACL_GPIO_49_OFFSET    1
#define    RTL8367D_ACL_GPIO_49_MASK    0x2
#define    RTL8367D_ACL_GPIO_48_OFFSET    0
#define    RTL8367D_ACL_GPIO_48_MASK    0x1

#define    RTL8367D_REG_UPS_CTRL0    0x1362
#define    RTL8367D_P3_REF_SD_BIT0_OFFSET    8
#define    RTL8367D_P3_REF_SD_BIT0_MASK    0xFF00
#define    RTL8367D_P2_REF_SD_OFFSET    0
#define    RTL8367D_P2_REF_SD_MASK    0xFF

#define    RTL8367D_REG_UPS_CTRL1    0x1363
#define    RTL8367D_UPS_OUT_OFFSET    8
#define    RTL8367D_UPS_OUT_MASK    0xFF00
#define    RTL8367D_FRC_SLOW_DOWN_EN_OFFSET    7
#define    RTL8367D_FRC_SLOW_DOWN_EN_MASK    0x80
#define    RTL8367D_UPS_WRITE_PULSE_OFFSET    1
#define    RTL8367D_UPS_WRITE_PULSE_MASK    0x2
#define    RTL8367D_UPS_EN_OFFSET    0
#define    RTL8367D_UPS_EN_MASK    0x1

#define    RTL8367D_REG_UPS_CTRL2    0x1364
#define    RTL8367D_IGNOE_MAC5_LINK_OFFSET    15
#define    RTL8367D_IGNOE_MAC5_LINK_MASK    0x8000
#define    RTL8367D_AGREE_SLEEP_OFFSET    14
#define    RTL8367D_AGREE_SLEEP_MASK    0x4000
#define    RTL8367D_WAIT_FOR_AGREEMENT_OFFSET    13
#define    RTL8367D_WAIT_FOR_AGREEMENT_MASK    0x2000
#define    RTL8367D_WAKE_UP_BY_LINK_OFFSET    12
#define    RTL8367D_WAKE_UP_BY_LINK_MASK    0x1000
#define    RTL8367D_WAKE_UP_BY_PHY_OFFSET    11
#define    RTL8367D_WAKE_UP_BY_PHY_MASK    0x800
#define    RTL8367D_SLOW_CLK_TGL_RATE_OFFSET    7
#define    RTL8367D_SLOW_CLK_TGL_RATE_MASK    0x780
#define    RTL8367D_PLL_G1_CTRL_EN_OFFSET    6
#define    RTL8367D_PLL_G1_CTRL_EN_MASK    0x40
#define    RTL8367D_PLL_G0_CTRL_EN_OFFSET    5
#define    RTL8367D_PLL_G0_CTRL_EN_MASK    0x20
#define    RTL8367D_SLOW_DOWN_PLL_EN_OFFSET    4
#define    RTL8367D_SLOW_DOWN_PLL_EN_MASK    0x10
#define    RTL8367D_SLOW_DOWN_CLK_EN_OFFSET    3
#define    RTL8367D_SLOW_DOWN_CLK_EN_MASK    0x8
#define    RTL8367D_GATING_CLK_SDS_EN_OFFSET    2
#define    RTL8367D_GATING_CLK_SDS_EN_MASK    0x4
#define    RTL8367D_GATING_CLK_CHIP_EN_OFFSET    1
#define    RTL8367D_GATING_CLK_CHIP_EN_MASK    0x2
#define    RTL8367D_GATING_SW_EN_OFFSET    0
#define    RTL8367D_GATING_SW_EN_MASK    0x1

#define    RTL8367D_REG_GATING_CLK_1    0x1365
#define    RTL8367D_ALDPS_MODE_4_OFFSET    15
#define    RTL8367D_ALDPS_MODE_4_MASK    0x8000
#define    RTL8367D_ALDPS_MODE_3_OFFSET    14
#define    RTL8367D_ALDPS_MODE_3_MASK    0x4000
#define    RTL8367D_ALDPS_MODE_2_OFFSET    13
#define    RTL8367D_ALDPS_MODE_2_MASK    0x2000
#define    RTL8367D_ALDPS_MODE_1_OFFSET    12
#define    RTL8367D_ALDPS_MODE_1_MASK    0x1000
#define    RTL8367D_ALDPS_MODE_0_OFFSET    11
#define    RTL8367D_ALDPS_MODE_0_MASK    0x800
#define    RTL8367D_UPS_DBGO_OFFSET    10
#define    RTL8367D_UPS_DBGO_MASK    0x400
#define    RTL8367D_IFMX_AFF_NOT_FF_OUT_OFFSET    9
#define    RTL8367D_IFMX_AFF_NOT_FF_OUT_MASK    0x200
#define    RTL8367D_WATER_LEVEL_FD_OFFSET    6
#define    RTL8367D_WATER_LEVEL_FD_MASK    0x1C0
#define    RTL8367D_WATER_LEVEL_Y2X_OFFSET    3
#define    RTL8367D_WATER_LEVEL_Y2X_MASK    0x38
#define    RTL8367D_WATER_LEVEL_X2Y_2_OFFSET    2
#define    RTL8367D_WATER_LEVEL_X2Y_2_MASK    0x4
#define    RTL8367D_IGNOE_MAC7_LINK_OFFSET    1
#define    RTL8367D_IGNOE_MAC7_LINK_MASK    0x2
#define    RTL8367D_IGNOE_MAC6_LINK_OFFSET    0
#define    RTL8367D_IGNOE_MAC6_LINK_MASK    0x1

#define    RTL8367D_REG_UPS_CTRL4    0x1366
#define    RTL8367D_PROB_EN_OFFSET    6
#define    RTL8367D_PROB_EN_MASK    0x40
#define    RTL8367D_PLL_DOWN_OFFSET    1
#define    RTL8367D_PLL_DOWN_MASK    0x2
#define    RTL8367D_XTAL_DOWN_OFFSET    0
#define    RTL8367D_XTAL_DOWN_MASK    0x1

#define    RTL8367D_REG_UPS_CTRL5    0x1367
#define    RTL8367D_FRC_CPU_ACPT_OFFSET    3
#define    RTL8367D_FRC_CPU_ACPT_MASK    0x8
#define    RTL8367D_UPS_CPU_ACPT_OFFSET    2
#define    RTL8367D_UPS_CPU_ACPT_MASK    0x4
#define    RTL8367D_UPS_DBG_4_OFFSET    0
#define    RTL8367D_UPS_DBG_4_MASK    0x3

#define    RTL8367D_REG_UPS_CTRL6    0x1368
#define    RTL8367D_UPS_CTRL6_OFFSET    0
#define    RTL8367D_UPS_CTRL6_MASK    0xF

#define    RTL8367D_REG_EFUSE_CMD    0x1370
#define    RTL8367D_CFG_DLYCMD_TIMER_OFFSET    10
#define    RTL8367D_CFG_DLYCMD_TIMER_MASK    0x7C00
#define    RTL8367D_CFG_DLYCMD_SEL_OFFSET    8
#define    RTL8367D_CFG_DLYCMD_SEL_MASK    0x300
#define    RTL8367D_EFUSE_TRMF_OFFSET    3
#define    RTL8367D_EFUSE_TRMF_MASK    0x18
#define    RTL8367D_EFUSE_ACCESS_BUSY_OFFSET    2
#define    RTL8367D_EFUSE_ACCESS_BUSY_MASK    0x4
#define    RTL8367D_EFUSE_COMMAND_EN_OFFSET    1
#define    RTL8367D_EFUSE_COMMAND_EN_MASK    0x2
#define    RTL8367D_EFUSE_WR_OFFSET    0
#define    RTL8367D_EFUSE_WR_MASK    0x1

#define    RTL8367D_REG_EFUSE_ADR    0x1371
#define    RTL8367D_DUMMY_15_10_OFFSET    8
#define    RTL8367D_DUMMY_15_10_MASK    0xFF00
#define    RTL8367D_EFUSE_ADDRESS_OFFSET    0
#define    RTL8367D_EFUSE_ADDRESS_MASK    0xFF

#define    RTL8367D_REG_EFUSE_WDAT    0x1372

#define    RTL8367D_REG_EFUSE_RDAT    0x1373

#define    RTL8367D_REG_I2C_CTRL    0x1374
#define    RTL8367D_MDX_MST_FAIL_LAT_OFFSET    1
#define    RTL8367D_MDX_MST_FAIL_LAT_MASK    0x2
#define    RTL8367D_MDX_MST_FAIL_CLRPS_OFFSET    0
#define    RTL8367D_MDX_MST_FAIL_CLRPS_MASK    0x1

#define    RTL8367D_REG_EEE_CFG    0x1375
#define    RTL8367D_CFG_BYPASS_GATELPTD_OFFSET    11
#define    RTL8367D_CFG_BYPASS_GATELPTD_MASK    0x800
#define    RTL8367D_EEE_ABT_ADDR2_OFFSET    6
#define    RTL8367D_EEE_ABT_ADDR2_MASK    0x7C0
#define    RTL8367D_EEE_ABT_ADDR1_OFFSET    1
#define    RTL8367D_EEE_ABT_ADDR1_MASK    0x3E
#define    RTL8367D_EEE_POLL_EN_OFFSET    0
#define    RTL8367D_EEE_POLL_EN_MASK    0x1

#define    RTL8367D_REG_EEE_PAGE    0x1376

#define    RTL8367D_REG_EEE_EXT_PAGE    0x1377

#define    RTL8367D_REG_EEE_EN_SPD1000    0x1378

#define    RTL8367D_REG_EEE_EN_SPD100    0x1379

#define    RTL8367D_REG_EEE_LP_SPD1000    0x137a

#define    RTL8367D_REG_EEE_LP_SPD100    0x137b

#define    RTL8367D_REG_DW8051_PRO_REG0    0x13a0

#define    RTL8367D_REG_DW8051_PRO_REG1    0x13a1

#define    RTL8367D_REG_DW8051_PRO_REG2    0x13a2

#define    RTL8367D_REG_DW8051_PRO_REG3    0x13a3

#define    RTL8367D_REG_DW8051_PRO_REG4    0x13a4

#define    RTL8367D_REG_DW8051_PRO_REG5    0x13a5

#define    RTL8367D_REG_DW8051_PRO_REG6    0x13a6

#define    RTL8367D_REG_DW8051_PRO_REG7    0x13a7

#define    RTL8367D_REG_EXT1_RXFIFO    0x13b0
#define    RTL8367D_EXT1_RXFIFO_ERR_CNT_OFFSET    12
#define    RTL8367D_EXT1_RXFIFO_ERR_CNT_MASK    0xF000
#define    RTL8367D_EXT1_RXFIFO_CLR_ERR_CNT_OFFSET    10
#define    RTL8367D_EXT1_RXFIFO_CLR_ERR_CNT_MASK    0x400
#define    RTL8367D_EXT1_RXFIFO_CFG_EDPTR_CHK_OFFSET    9
#define    RTL8367D_EXT1_RXFIFO_CFG_EDPTR_CHK_MASK    0x200
#define    RTL8367D_EXT1_RXFIFO_CFG_BGPTR_CHK_OFFSET    8
#define    RTL8367D_EXT1_RXFIFO_CFG_BGPTR_CHK_MASK    0x100
#define    RTL8367D_EXT1_RXFIFO_CFG_AFO_IPG_CNT_OFFSET    4
#define    RTL8367D_EXT1_RXFIFO_CFG_AFO_IPG_CNT_MASK    0xF0
#define    RTL8367D_EXT1_RXFIFO_CFG_AFO_IPGCOMP_OFFSET    3
#define    RTL8367D_EXT1_RXFIFO_CFG_AFO_IPGCOMP_MASK    0x8
#define    RTL8367D_EXT1_RXFIFO_CFG_WATER_LEVEL_OFFSET    0
#define    RTL8367D_EXT1_RXFIFO_CFG_WATER_LEVEL_MASK    0x7

#define    RTL8367D_REG_EXT1_TXFIFO    0x13b1
#define    RTL8367D_EXT1_TXFIFO_ERR_CNT_OFFSET    12
#define    RTL8367D_EXT1_TXFIFO_ERR_CNT_MASK    0xF000
#define    RTL8367D_EXT1_TXFIFO_CLR_ERR_CNT_OFFSET    10
#define    RTL8367D_EXT1_TXFIFO_CLR_ERR_CNT_MASK    0x400
#define    RTL8367D_EXT1_TXFIFO_CFG_EDPTR_CHK_OFFSET    9
#define    RTL8367D_EXT1_TXFIFO_CFG_EDPTR_CHK_MASK    0x200
#define    RTL8367D_EXT1_TXFIFO_CFG_BGPTR_CHK_OFFSET    8
#define    RTL8367D_EXT1_TXFIFO_CFG_BGPTR_CHK_MASK    0x100
#define    RTL8367D_EXT1_TXFIFO_CFG_AFO_IPG_CNT_OFFSET    4
#define    RTL8367D_EXT1_TXFIFO_CFG_AFO_IPG_CNT_MASK    0xF0
#define    RTL8367D_EXT1_TXFIFO_CFG_AFO_IPGCOMP_OFFSET    3
#define    RTL8367D_EXT1_TXFIFO_CFG_AFO_IPGCOMP_MASK    0x8
#define    RTL8367D_EXT1_TXFIFO_CFG_WATER_LEVEL_OFFSET    0
#define    RTL8367D_EXT1_TXFIFO_CFG_WATER_LEVEL_MASK    0x7

#define    RTL8367D_REG_PROTECT_ID    0x13c0

#define    RTL8367D_REG_CHIP_VER_INTL    0x13c1
#define    RTL8367D_CHIP_VER_INTL_OFFSET    0
#define    RTL8367D_CHIP_VER_INTL_MASK    0xF

#define    RTL8367D_REG_MAGIC_ID    0x13c2

#define    RTL8367D_REG_DIGITAL_INTERFACE_SELECT_1    0x13c3
#define    RTL8367D_SKIP_MII_2_RXER_OFFSET    4
#define    RTL8367D_SKIP_MII_2_RXER_MASK    0x10
#define    RTL8367D_SELECT_GMII_2_OFFSET    0
#define    RTL8367D_SELECT_GMII_2_MASK    0xF

#define    RTL8367D_REG_EXT2_RGMXF    0x13c5
#define    RTL8367D_EXT2_RGTX_INV_OFFSET    6
#define    RTL8367D_EXT2_RGTX_INV_MASK    0x40
#define    RTL8367D_EXT2_RGRX_INV_OFFSET    5
#define    RTL8367D_EXT2_RGRX_INV_MASK    0x20
#define    RTL8367D_EXT2_RGMXF_OFFSET    0
#define    RTL8367D_EXT2_RGMXF_MASK    0x1F

#define    RTL8367D_REG_ROUTER_UPS_CFG    0x13c6
#define    RTL8367D_UPS_Status_OFFSET    1
#define    RTL8367D_UPS_Status_MASK    0x2
#define    RTL8367D_SoftStart_OFFSET    0
#define    RTL8367D_SoftStart_MASK    0x1

#define    RTL8367D_REG_STOP_COUNT_TX_MIB    0x13e0
#define    RTL8367D_CFG_STOP_CNTTX_MIB_OFFSET    8
#define    RTL8367D_CFG_STOP_CNTTX_MIB_MASK    0x100
#define    RTL8367D_EN_RTT2_L_OFFSET    5
#define    RTL8367D_EN_RTT2_L_MASK    0x20
#define    RTL8367D_EN_RTT1_L_OFFSET    4
#define    RTL8367D_EN_RTT1_L_MASK    0x10

#define    RTL8367D_REG_LED_DRI_CFG    0x13e1
#define    RTL8367D_ORG_COL_EXT_OFFSET    3
#define    RTL8367D_ORG_COL_EXT_MASK    0x8
#define    RTL8367D_ORG_CRS_EXT_OFFSET    2
#define    RTL8367D_ORG_CRS_EXT_MASK    0x4
#define    RTL8367D_G1_WAKE_STYLE_OFFSET    1
#define    RTL8367D_G1_WAKE_STYLE_MASK    0x2
#define    RTL8367D_LED_DRIVING_OFFSET    0
#define    RTL8367D_LED_DRIVING_MASK    0x1

#define    RTL8367D_REG_CHIP_DEBUG2    0x13e2
#define    RTL8367D_RG2_DN_OFFSET    6
#define    RTL8367D_RG2_DN_MASK    0x1C0
#define    RTL8367D_RG2_DP_OFFSET    3
#define    RTL8367D_RG2_DP_MASK    0x38
#define    RTL8367D_DRI_EXT2_RG_OFFSET    2
#define    RTL8367D_DRI_EXT2_RG_MASK    0x4
#define    RTL8367D_DRI_EXT2_OFFSET    1
#define    RTL8367D_DRI_EXT2_MASK    0x2
#define    RTL8367D_SLR_EXt2_OFFSET    0
#define    RTL8367D_SLR_EXt2_MASK    0x1

#define    RTL8367D_REG_DIGITAL_DEBUG_2    0x13e3

#define    RTL8367D_REG_FIBER_RTL_OUI_CFG0    0x13e4
#define    RTL8367D_FIBER_RTL_OUI_CFG0_OFFSET    0
#define    RTL8367D_FIBER_RTL_OUI_CFG0_MASK    0xFF

#define    RTL8367D_REG_FIBER_RTL_OUI_CFG1    0x13e5

#define    RTL8367D_REG_FIBER_CFG_0    0x13e6
#define    RTL8367D_REV_NUM_OFFSET    8
#define    RTL8367D_REV_NUM_MASK    0xF00
#define    RTL8367D_MODEL_NUM_OFFSET    0
#define    RTL8367D_MODEL_NUM_MASK    0x3F

#define    RTL8367D_REG_FIBER_CFG_1    0x13e7
#define    RTL8367D_FIBER_CFG_1_OFFSET    5
#define    RTL8367D_FIBER_CFG_1_MASK    0x20

#define    RTL8367D_REG_FIBER_CFG_2    0x13e8
#define    RTL8367D_SEL_SDET_PS_OFFSET    12
#define    RTL8367D_SEL_SDET_PS_MASK    0xF000
#define    RTL8367D_UTP_DIS_RX_OFFSET    10
#define    RTL8367D_UTP_DIS_RX_MASK    0xC00
#define    RTL8367D_UTP_FRC_LD_OFFSET    8
#define    RTL8367D_UTP_FRC_LD_MASK    0x300
#define    RTL8367D_SDS_RX_DISABLE_OFFSET    6
#define    RTL8367D_SDS_RX_DISABLE_MASK    0xC0
#define    RTL8367D_SDS_TX_DISABLE_OFFSET    4
#define    RTL8367D_SDS_TX_DISABLE_MASK    0x30
#define    RTL8367D_SDS_PWR_ISO_OFFSET    2
#define    RTL8367D_SDS_PWR_ISO_MASK    0xC
#define    RTL8367D_SDS_FRC_LD_OFFSET    0
#define    RTL8367D_SDS_FRC_LD_MASK    0x3

#define    RTL8367D_REG_FIBER_CFG_3    0x13e9
#define    RTL8367D_FIBER_CFG_3_OFFSET    0
#define    RTL8367D_FIBER_CFG_3_MASK    0xFFF

#define    RTL8367D_REG_FIBER_CFG_4    0x13ea

#define    RTL8367D_REG_UTP_FIB_DET    0x13eb
#define    RTL8367D_FORCE_SEL_FIBER_OFFSET    14
#define    RTL8367D_FORCE_SEL_FIBER_MASK    0xC000
#define    RTL8367D_FIB_FINAL_TIMER_OFFSET    12
#define    RTL8367D_FIB_FINAL_TIMER_MASK    0x3000
#define    RTL8367D_FIB_LINK_TIMER_OFFSET    10
#define    RTL8367D_FIB_LINK_TIMER_MASK    0xC00
#define    RTL8367D_FIB_SDET_TIMER_OFFSET    8
#define    RTL8367D_FIB_SDET_TIMER_MASK    0x300
#define    RTL8367D_UTP_LINK_TIMER_OFFSET    6
#define    RTL8367D_UTP_LINK_TIMER_MASK    0xC0
#define    RTL8367D_UTP_SDET_TIMER_OFFSET    4
#define    RTL8367D_UTP_SDET_TIMER_MASK    0x30
#define    RTL8367D_FORCE_AUTODET_OFFSET    3
#define    RTL8367D_FORCE_AUTODET_MASK    0x8
#define    RTL8367D_AUTODET_FSM_CLR_OFFSET    2
#define    RTL8367D_AUTODET_FSM_CLR_MASK    0x4
#define    RTL8367D_UTP_FIRST_OFFSET    1
#define    RTL8367D_UTP_FIRST_MASK    0x2
#define    RTL8367D_UTP_FIB_DISAUTODET_OFFSET    0
#define    RTL8367D_UTP_FIB_DISAUTODET_MASK    0x1

#define    RTL8367D_REG_NRESTORE_MAGIC_NUM    0x13ec
#define    RTL8367D_NRESTORE_MAGIC_NUM_MASK    0xFFFF
#define    RTL8367D_EEPROM_PROGRAM_CYCLE_OFFSET    0
#define    RTL8367D_EEPROM_PROGRAM_CYCLE_MASK    0x3

#define    RTL8367D_REG_MAC_ACTIVE    0x13ee
#define    RTL8367D_FRC_MAC_ACTIVE_OFFSET    8
#define    RTL8367D_FRC_MAC_ACTIVE_MASK    0x100
#define    RTL8367D_MAC_ACTIVE_OFFSET    0
#define    RTL8367D_MAC_ACTIVE_MASK    0xFF

#define    RTL8367D_REG_SERDES_RESULT    0x13ef
#define    RTL8367D_FIB100_DET_OFFSET    4
#define    RTL8367D_FIB100_DET_MASK    0x10
#define    RTL8367D_FIB_ISO_OFFSET    3
#define    RTL8367D_FIB_ISO_MASK    0x8
#define    RTL8367D_SDS_ANFAULT_OFFSET    2
#define    RTL8367D_SDS_ANFAULT_MASK    0x4
#define    RTL8367D_SDS_INTB_OFFSET    1
#define    RTL8367D_SDS_INTB_MASK    0x2
#define    RTL8367D_SDS_LINK_OK_OFFSET    0
#define    RTL8367D_SDS_LINK_OK_MASK    0x1

#define    RTL8367D_REG_CHIP_ECO    0x13f0
#define    RTL8367D_CFG_CHIP_ECO_OFFSET    1
#define    RTL8367D_CFG_CHIP_ECO_MASK    0xFFFE
#define    RTL8367D_CFG_CKOUTEN_OFFSET    0
#define    RTL8367D_CFG_CKOUTEN_MASK    0x1

#define    RTL8367D_REG_WAKELPI_SLOT_PRD    0x13f1
#define    RTL8367D_WAKELPI_SLOT_PRD_OFFSET    0
#define    RTL8367D_WAKELPI_SLOT_PRD_MASK    0x1F

#define    RTL8367D_REG_WAKELPI_SLOT_PG0    0x13f2
#define    RTL8367D_WAKELPI_SLOT_P1_OFFSET    8
#define    RTL8367D_WAKELPI_SLOT_P1_MASK    0x1F00
#define    RTL8367D_WAKELPI_SLOT_P0_OFFSET    0
#define    RTL8367D_WAKELPI_SLOT_P0_MASK    0x1F

#define    RTL8367D_REG_WAKELPI_SLOT_PG1    0x13f3
#define    RTL8367D_WAKELPI_SLOT_P3_OFFSET    8
#define    RTL8367D_WAKELPI_SLOT_P3_MASK    0x1F00
#define    RTL8367D_WAKELPI_SLOT_P2_OFFSET    0
#define    RTL8367D_WAKELPI_SLOT_P2_MASK    0x1F

#define    RTL8367D_REG_WAKELPI_SLOT_PG2    0x13f4
#define    RTL8367D_WAKELPI_SLOT_P5_OFFSET    8
#define    RTL8367D_WAKELPI_SLOT_P5_MASK    0x1F00
#define    RTL8367D_WAKELPI_SLOT_P4_OFFSET    0
#define    RTL8367D_WAKELPI_SLOT_P4_MASK    0x1F

#define    RTL8367D_REG_WAKELPI_SLOT_PG3    0x13f5
#define    RTL8367D_WAKELPI_SLOT_P7_OFFSET    8
#define    RTL8367D_WAKELPI_SLOT_P7_MASK    0x1F00
#define    RTL8367D_WAKELPI_SLOT_P6_OFFSET    0
#define    RTL8367D_WAKELPI_SLOT_P6_MASK    0x1F

#define    RTL8367D_REG_SYNC_FIFO_0    0x13f6
#define    RTL8367D_SYNC_FIFO_TX_OFFSET    8
#define    RTL8367D_SYNC_FIFO_TX_MASK    0x700
#define    RTL8367D_SYNC_FIFO_RX_OFFSET    0
#define    RTL8367D_SYNC_FIFO_RX_MASK    0xFF

#define    RTL8367D_REG_SYNC_FIFO_1    0x13f7
#define    RTL8367D_SYNC_FIFO_TX_ERR_OFFSET    8
#define    RTL8367D_SYNC_FIFO_TX_ERR_MASK    0x700
#define    RTL8367D_SYNC_FIFO_RX_ERR_OFFSET    0
#define    RTL8367D_SYNC_FIFO_RX_ERR_MASK    0xFF

#define    RTL8367D_REG_RGM_EEE    0x13f8
#define    RTL8367D_EXT2_PAD_STOP_EN_OFFSET    14
#define    RTL8367D_EXT2_PAD_STOP_EN_MASK    0x4000
#define    RTL8367D_EXT1_PAD_STOP_EN_OFFSET    13
#define    RTL8367D_EXT1_PAD_STOP_EN_MASK    0x2000
#define    RTL8367D_EXT0_PAD_STOP_EN_OFFSET    12
#define    RTL8367D_EXT0_PAD_STOP_EN_MASK    0x1000
#define    RTL8367D_EXT2_CYCLE_PAD_OFFSET    8
#define    RTL8367D_EXT2_CYCLE_PAD_MASK    0xF00
#define    RTL8367D_EXT1_CYCLE_PAD_OFFSET    4
#define    RTL8367D_EXT1_CYCLE_PAD_MASK    0xF0
#define    RTL8367D_EXT0_CYCLE_PAD_OFFSET    0
#define    RTL8367D_EXT0_CYCLE_PAD_MASK    0xF

#define    RTL8367D_REG_EXT_TXC_DLY    0x13f9
#define    RTL8367D_EXT1_GMII_TX_DELAY_OFFSET    12
#define    RTL8367D_EXT1_GMII_TX_DELAY_MASK    0x7000
#define    RTL8367D_EXT0_GMII_TX_DELAY_OFFSET    9
#define    RTL8367D_EXT0_GMII_TX_DELAY_MASK    0xE00
#define    RTL8367D_EXT2_RGMII_TX_DELAY_OFFSET    6
#define    RTL8367D_EXT2_RGMII_TX_DELAY_MASK    0x1C0
#define    RTL8367D_EXT1_RGMII_TX_DELAY_OFFSET    3
#define    RTL8367D_EXT1_RGMII_TX_DELAY_MASK    0x38
#define    RTL8367D_EXT0_RGMII_TX_DELAY_OFFSET    0
#define    RTL8367D_EXT0_RGMII_TX_DELAY_MASK    0x7

#define    RTL8367D_REG_CHIP_DUMMY_NO    0x13fb
#define    RTL8367D_CHIP_DUMMY_NO_OFFSET    0
#define    RTL8367D_CHIP_DUMMY_NO_MASK    0xF

#define    RTL8367D_REG_EFUSE_CHK_0    0x13fc
#define    RTL8367D_EFUSE_CHK_STOP_ADR_OFFSET    8
#define    RTL8367D_EFUSE_CHK_STOP_ADR_MASK    0xFF00
#define    RTL8367D_EFUSE_CHK_FAIL_OFFSET    2
#define    RTL8367D_EFUSE_CHK_FAIL_MASK    0x4
#define    RTL8367D_EFUSE_CHK_DONE_OFFSET    1
#define    RTL8367D_EFUSE_CHK_DONE_MASK    0x2
#define    RTL8367D_EFUSE_CHK_0_EFUSE_CHK_PS_OFFSET    0
#define    RTL8367D_EFUSE_CHK_0_EFUSE_CHK_PS_MASK    0x1

#define    RTL8367D_REG_EFUSE_CHK_1    0x13fd
#define    RTL8367D_EFUSE_CHK_END_OFFSET    8
#define    RTL8367D_EFUSE_CHK_END_MASK    0xFF00
#define    RTL8367D_EFUSE_CHK_BGN_OFFSET    0
#define    RTL8367D_EFUSE_CHK_BGN_MASK    0xFF

#define    RTL8367D_REG_EFUSE_CHK_2    0x13fe

/* (16'h1400)mtrpool_reg */

#define    RTL8367D_REG_METER0_RATE_CTRL0    0x1400

#define    RTL8367D_REG_METER0_RATE_CTRL1    0x1401
#define    RTL8367D_METER0_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER0_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER1_RATE_CTRL0    0x1402

#define    RTL8367D_REG_METER1_RATE_CTRL1    0x1403
#define    RTL8367D_METER1_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER1_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER2_RATE_CTRL0    0x1404

#define    RTL8367D_REG_METER2_RATE_CTRL1    0x1405
#define    RTL8367D_METER2_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER2_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER3_RATE_CTRL0    0x1406

#define    RTL8367D_REG_METER3_RATE_CTRL1    0x1407
#define    RTL8367D_METER3_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER3_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER4_RATE_CTRL0    0x1408

#define    RTL8367D_REG_METER4_RATE_CTRL1    0x1409
#define    RTL8367D_METER4_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER4_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER5_RATE_CTRL0    0x140a

#define    RTL8367D_REG_METER5_RATE_CTRL1    0x140b
#define    RTL8367D_METER5_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER5_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER6_RATE_CTRL0    0x140c

#define    RTL8367D_REG_METER6_RATE_CTRL1    0x140d
#define    RTL8367D_METER6_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER6_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER7_RATE_CTRL0    0x140e

#define    RTL8367D_REG_METER7_RATE_CTRL1    0x140f
#define    RTL8367D_METER7_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER7_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER8_RATE_CTRL0    0x1410

#define    RTL8367D_REG_METER8_RATE_CTRL1    0x1411
#define    RTL8367D_METER8_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER8_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER9_RATE_CTRL0    0x1412

#define    RTL8367D_REG_METER9_RATE_CTRL1    0x1413
#define    RTL8367D_METER9_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER9_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER10_RATE_CTRL0    0x1414

#define    RTL8367D_REG_METER10_RATE_CTRL1    0x1415
#define    RTL8367D_METER10_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER10_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER11_RATE_CTRL0    0x1416

#define    RTL8367D_REG_METER11_RATE_CTRL1    0x1417
#define    RTL8367D_METER11_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER11_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER12_RATE_CTRL0    0x1418

#define    RTL8367D_REG_METER12_RATE_CTRL1    0x1419
#define    RTL8367D_METER12_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER12_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER13_RATE_CTRL0    0x141a

#define    RTL8367D_REG_METER13_RATE_CTRL1    0x141b
#define    RTL8367D_METER13_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER13_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER14_RATE_CTRL0    0x141c

#define    RTL8367D_REG_METER14_RATE_CTRL1    0x141d
#define    RTL8367D_METER14_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER14_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER15_RATE_CTRL0    0x141e

#define    RTL8367D_REG_METER15_RATE_CTRL1    0x141f
#define    RTL8367D_METER15_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER15_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER16_RATE_CTRL0    0x1420

#define    RTL8367D_REG_METER16_RATE_CTRL1    0x1421
#define    RTL8367D_METER16_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER16_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER17_RATE_CTRL0    0x1422

#define    RTL8367D_REG_METER17_RATE_CTRL1    0x1423
#define    RTL8367D_METER17_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER17_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER18_RATE_CTRL0    0x1424

#define    RTL8367D_REG_METER18_RATE_CTRL1    0x1425
#define    RTL8367D_METER18_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER18_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER19_RATE_CTRL0    0x1426

#define    RTL8367D_REG_METER19_RATE_CTRL1    0x1427
#define    RTL8367D_METER19_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER19_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER20_RATE_CTRL0    0x1428

#define    RTL8367D_REG_METER20_RATE_CTRL1    0x1429
#define    RTL8367D_METER20_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER20_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER21_RATE_CTRL0    0x142a

#define    RTL8367D_REG_METER21_RATE_CTRL1    0x142b
#define    RTL8367D_METER21_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER21_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER22_RATE_CTRL0    0x142c

#define    RTL8367D_REG_METER22_RATE_CTRL1    0x142d
#define    RTL8367D_METER22_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER22_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER23_RATE_CTRL0    0x142e

#define    RTL8367D_REG_METER23_RATE_CTRL1    0x142f
#define    RTL8367D_METER23_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER23_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER24_RATE_CTRL0    0x1430

#define    RTL8367D_REG_METER24_RATE_CTRL1    0x1431
#define    RTL8367D_METER24_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER24_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER25_RATE_CTRL0    0x1432

#define    RTL8367D_REG_METER25_RATE_CTRL1    0x1433
#define    RTL8367D_METER25_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER25_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER26_RATE_CTRL0    0x1434

#define    RTL8367D_REG_METER26_RATE_CTRL1    0x1435
#define    RTL8367D_METER26_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER26_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER27_RATE_CTRL0    0x1436

#define    RTL8367D_REG_METER27_RATE_CTRL1    0x1437
#define    RTL8367D_METER27_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER27_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER28_RATE_CTRL0    0x1438

#define    RTL8367D_REG_METER28_RATE_CTRL1    0x1439
#define    RTL8367D_METER28_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER28_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER29_RATE_CTRL0    0x143a

#define    RTL8367D_REG_METER29_RATE_CTRL1    0x143b
#define    RTL8367D_METER29_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER29_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER30_RATE_CTRL0    0x143c

#define    RTL8367D_REG_METER30_RATE_CTRL1    0x143d
#define    RTL8367D_METER30_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER30_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER31_RATE_CTRL0    0x143e

#define    RTL8367D_REG_METER31_RATE_CTRL1    0x143f
#define    RTL8367D_METER31_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER31_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER32_RATE_CTRL0    0x1440

#define    RTL8367D_REG_METER32_RATE_CTRL1    0x1441
#define    RTL8367D_METER32_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER32_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER33_RATE_CTRL0    0x1442

#define    RTL8367D_REG_METER33_RATE_CTRL1    0x1443
#define    RTL8367D_METER33_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER33_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER34_RATE_CTRL0    0x1444

#define    RTL8367D_REG_METER34_RATE_CTRL1    0x1445
#define    RTL8367D_METER34_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER34_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER35_RATE_CTRL0    0x1446

#define    RTL8367D_REG_METER35_RATE_CTRL1    0x1447
#define    RTL8367D_METER35_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER35_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER36_RATE_CTRL0    0x1448

#define    RTL8367D_REG_METER36_RATE_CTRL1    0x1449
#define    RTL8367D_METER36_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER36_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER37_RATE_CTRL0    0x144a

#define    RTL8367D_REG_METER37_RATE_CTRL1    0x144b
#define    RTL8367D_METER37_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER37_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER38_RATE_CTRL0    0x144c

#define    RTL8367D_REG_METER38_RATE_CTRL1    0x144d
#define    RTL8367D_METER38_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER38_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER39_RATE_CTRL0    0x144e

#define    RTL8367D_REG_METER39_RATE_CTRL1    0x144f
#define    RTL8367D_METER39_RATE_CTRL1_OFFSET    0
#define    RTL8367D_METER39_RATE_CTRL1_MASK    0x7

#define    RTL8367D_REG_METER_MODE_SETTING0    0x1460

#define    RTL8367D_REG_METER_MODE_SETTING1    0x1461

#define    RTL8367D_REG_METER_MODE_SETTING2    0x1462
#define    RTL8367D_METER_MODE_SETTING2_OFFSET    0
#define    RTL8367D_METER_MODE_SETTING2_MASK    0xFF

#define    RTL8367D_REG_METER_MODE_TOKEN_CFG    0x1463
#define    RTL8367D_METER_MODE_TOKEN_CFG_OFFSET    0
#define    RTL8367D_METER_MODE_TOKEN_CFG_MASK    0x7FF

#define    RTL8367D_REG_METER0_BUCKET_SIZE    0x1600

#define    RTL8367D_REG_METER1_BUCKET_SIZE    0x1601

#define    RTL8367D_REG_METER2_BUCKET_SIZE    0x1602

#define    RTL8367D_REG_METER3_BUCKET_SIZE    0x1603

#define    RTL8367D_REG_METER4_BUCKET_SIZE    0x1604

#define    RTL8367D_REG_METER5_BUCKET_SIZE    0x1605

#define    RTL8367D_REG_METER6_BUCKET_SIZE    0x1606

#define    RTL8367D_REG_METER7_BUCKET_SIZE    0x1607

#define    RTL8367D_REG_METER8_BUCKET_SIZE    0x1608

#define    RTL8367D_REG_METER9_BUCKET_SIZE    0x1609

#define    RTL8367D_REG_METER10_BUCKET_SIZE    0x160a

#define    RTL8367D_REG_METER11_BUCKET_SIZE    0x160b

#define    RTL8367D_REG_METER12_BUCKET_SIZE    0x160c

#define    RTL8367D_REG_METER13_BUCKET_SIZE    0x160d

#define    RTL8367D_REG_METER14_BUCKET_SIZE    0x160e

#define    RTL8367D_REG_METER15_BUCKET_SIZE    0x160f

#define    RTL8367D_REG_METER16_BUCKET_SIZE    0x1610

#define    RTL8367D_REG_METER17_BUCKET_SIZE    0x1611

#define    RTL8367D_REG_METER18_BUCKET_SIZE    0x1612

#define    RTL8367D_REG_METER19_BUCKET_SIZE    0x1613

#define    RTL8367D_REG_METER20_BUCKET_SIZE    0x1614

#define    RTL8367D_REG_METER21_BUCKET_SIZE    0x1615

#define    RTL8367D_REG_METER22_BUCKET_SIZE    0x1616

#define    RTL8367D_REG_METER23_BUCKET_SIZE    0x1617

#define    RTL8367D_REG_METER24_BUCKET_SIZE    0x1618

#define    RTL8367D_REG_METER25_BUCKET_SIZE    0x1619

#define    RTL8367D_REG_METER26_BUCKET_SIZE    0x161a

#define    RTL8367D_REG_METER27_BUCKET_SIZE    0x161b

#define    RTL8367D_REG_METER28_BUCKET_SIZE    0x161c

#define    RTL8367D_REG_METER29_BUCKET_SIZE    0x161d

#define    RTL8367D_REG_METER30_BUCKET_SIZE    0x161e

#define    RTL8367D_REG_METER31_BUCKET_SIZE    0x161f

#define    RTL8367D_REG_METER32_BUCKET_SIZE    0x1620

#define    RTL8367D_REG_METER33_BUCKET_SIZE    0x1621

#define    RTL8367D_REG_METER34_BUCKET_SIZE    0x1622

#define    RTL8367D_REG_METER35_BUCKET_SIZE    0x1623

#define    RTL8367D_REG_METER36_BUCKET_SIZE    0x1624

#define    RTL8367D_REG_METER37_BUCKET_SIZE    0x1625

#define    RTL8367D_REG_METER38_BUCKET_SIZE    0x1626

#define    RTL8367D_REG_METER39_BUCKET_SIZE    0x1627

#define    RTL8367D_REG_METER_CTRL0    0x1700
#define    RTL8367D_METER_OP_OFFSET    8
#define    RTL8367D_METER_OP_MASK    0x100
#define    RTL8367D_METER_TICK_OFFSET    0
#define    RTL8367D_METER_TICK_MASK    0xFF

#define    RTL8367D_REG_METER_CTRL1    0x1701
#define    RTL8367D_METER_CTRL1_OFFSET    0
#define    RTL8367D_METER_CTRL1_MASK    0xFF

#define    RTL8367D_REG_METER_OVERRATE_INDICATOR0    0x1702

#define    RTL8367D_REG_METER_OVERRATE_INDICATOR1    0x1703

#define    RTL8367D_REG_METER_OVERRATE_INDICATOR2    0x1704
#define    RTL8367D_METER_OVERRATE_INDICATOR2_OFFSET    0
#define    RTL8367D_METER_OVERRATE_INDICATOR2_MASK    0xFF

#define    RTL8367D_REG_METER_OVERRATE_INDICATOR0_8051    0x1705

#define    RTL8367D_REG_METER_OVERRATE_INDICATOR1_8051    0x1706

#define    RTL8367D_REG_METER_OVERRATE_INDICATOR2_8051    0x1707
#define    RTL8367D_METER_OVERRATE_INDICATOR2_8051_OFFSET    0
#define    RTL8367D_METER_OVERRATE_INDICATOR2_8051_MASK    0xFF

#define    RTL8367D_REG_METER_IFG_CTRL0    0x1712
#define    RTL8367D_METER15_IFG_OFFSET    15
#define    RTL8367D_METER15_IFG_MASK    0x8000
#define    RTL8367D_METER14_IFG_OFFSET    14
#define    RTL8367D_METER14_IFG_MASK    0x4000
#define    RTL8367D_METER13_IFG_OFFSET    13
#define    RTL8367D_METER13_IFG_MASK    0x2000
#define    RTL8367D_METER12_IFG_OFFSET    12
#define    RTL8367D_METER12_IFG_MASK    0x1000
#define    RTL8367D_METER11_IFG_OFFSET    11
#define    RTL8367D_METER11_IFG_MASK    0x800
#define    RTL8367D_METER10_IFG_OFFSET    10
#define    RTL8367D_METER10_IFG_MASK    0x400
#define    RTL8367D_METER9_IFG_OFFSET    9
#define    RTL8367D_METER9_IFG_MASK    0x200
#define    RTL8367D_METER8_IFG_OFFSET    8
#define    RTL8367D_METER8_IFG_MASK    0x100
#define    RTL8367D_METER7_IFG_OFFSET    7
#define    RTL8367D_METER7_IFG_MASK    0x80
#define    RTL8367D_METER6_IFG_OFFSET    6
#define    RTL8367D_METER6_IFG_MASK    0x40
#define    RTL8367D_METER5_IFG_OFFSET    5
#define    RTL8367D_METER5_IFG_MASK    0x20
#define    RTL8367D_METER4_IFG_OFFSET    4
#define    RTL8367D_METER4_IFG_MASK    0x10
#define    RTL8367D_METER3_IFG_OFFSET    3
#define    RTL8367D_METER3_IFG_MASK    0x8
#define    RTL8367D_METER2_IFG_OFFSET    2
#define    RTL8367D_METER2_IFG_MASK    0x4
#define    RTL8367D_METER1_IFG_OFFSET    1
#define    RTL8367D_METER1_IFG_MASK    0x2
#define    RTL8367D_METER0_IFG_OFFSET    0
#define    RTL8367D_METER0_IFG_MASK    0x1

#define    RTL8367D_REG_METER_IFG_CTRL1    0x1713
#define    RTL8367D_METER31_IFG_OFFSET    15
#define    RTL8367D_METER31_IFG_MASK    0x8000
#define    RTL8367D_METER30_IFG_OFFSET    14
#define    RTL8367D_METER30_IFG_MASK    0x4000
#define    RTL8367D_METER29_IFG_OFFSET    13
#define    RTL8367D_METER29_IFG_MASK    0x2000
#define    RTL8367D_METER28_IFG_OFFSET    12
#define    RTL8367D_METER28_IFG_MASK    0x1000
#define    RTL8367D_METER27_IFG_OFFSET    11
#define    RTL8367D_METER27_IFG_MASK    0x800
#define    RTL8367D_METER26_IFG_OFFSET    10
#define    RTL8367D_METER26_IFG_MASK    0x400
#define    RTL8367D_METER25_IFG_OFFSET    9
#define    RTL8367D_METER25_IFG_MASK    0x200
#define    RTL8367D_METER24_IFG_OFFSET    8
#define    RTL8367D_METER24_IFG_MASK    0x100
#define    RTL8367D_METER23_IFG_OFFSET    7
#define    RTL8367D_METER23_IFG_MASK    0x80
#define    RTL8367D_METER22_IFG_OFFSET    6
#define    RTL8367D_METER22_IFG_MASK    0x40
#define    RTL8367D_METER21_IFG_OFFSET    5
#define    RTL8367D_METER21_IFG_MASK    0x20
#define    RTL8367D_METER20_IFG_OFFSET    4
#define    RTL8367D_METER20_IFG_MASK    0x10
#define    RTL8367D_METER19_IFG_OFFSET    3
#define    RTL8367D_METER19_IFG_MASK    0x8
#define    RTL8367D_METER18_IFG_OFFSET    2
#define    RTL8367D_METER18_IFG_MASK    0x4
#define    RTL8367D_METER17_IFG_OFFSET    1
#define    RTL8367D_METER17_IFG_MASK    0x2
#define    RTL8367D_METER16_IFG_OFFSET    0
#define    RTL8367D_METER16_IFG_MASK    0x1

#define    RTL8367D_REG_METER_IFG_CTRL2    0x1714
#define    RTL8367D_METER39_IFG_OFFSET    7
#define    RTL8367D_METER39_IFG_MASK    0x80
#define    RTL8367D_METER38_IFG_OFFSET    6
#define    RTL8367D_METER38_IFG_MASK    0x40
#define    RTL8367D_METER37_IFG_OFFSET    5
#define    RTL8367D_METER37_IFG_MASK    0x20
#define    RTL8367D_METER36_IFG_OFFSET    4
#define    RTL8367D_METER36_IFG_MASK    0x10
#define    RTL8367D_METER35_IFG_OFFSET    3
#define    RTL8367D_METER35_IFG_MASK    0x8
#define    RTL8367D_METER34_IFG_OFFSET    2
#define    RTL8367D_METER34_IFG_MASK    0x4
#define    RTL8367D_METER33_IFG_OFFSET    1
#define    RTL8367D_METER33_IFG_MASK    0x2
#define    RTL8367D_METER32_IFG_OFFSET    0
#define    RTL8367D_METER32_IFG_MASK    0x1

#define    RTL8367D_REG_METER_CTRL2    0x1722
#define    RTL8367D_cfg_mtr_tick_8g_OFFSET    8
#define    RTL8367D_cfg_mtr_tick_8g_MASK    0xFF00
#define    RTL8367D_cfg_mtr_dec_cnt_8g_OFFSET    0
#define    RTL8367D_cfg_mtr_dec_cnt_8g_MASK    0xFF

#define    RTL8367D_REG_METER_CTRL3    0x1723
#define    RTL8367D_cfg_mtr_tick_2hsg_OFFSET    8
#define    RTL8367D_cfg_mtr_tick_2hsg_MASK    0xFF00
#define    RTL8367D_cfg_mtr_dec_cnt_2hsg_OFFSET    0
#define    RTL8367D_cfg_mtr_dec_cnt_2hsg_MASK    0xFF

/* (16'h1800)8051_RLDP_EEE_reg */

#define    RTL8367D_REG_RLDP_CTRL0    0x18e0
#define    RTL8367D_RLDP_TRIGGER_MODE_OFFSET    14
#define    RTL8367D_RLDP_TRIGGER_MODE_MASK    0x4000
#define    RTL8367D_RLDP_FRC_LOOP_PORTMSK_OFFSET    6
#define    RTL8367D_RLDP_FRC_LOOP_PORTMSK_MASK    0x3FC0
#define    RTL8367D_RLDP_GEN_RANDOM_OFFSET    3
#define    RTL8367D_RLDP_GEN_RANDOM_MASK    0x8
#define    RTL8367D_RLDP_COMP_ID_OFFSET    2
#define    RTL8367D_RLDP_COMP_ID_MASK    0x4
#define    RTL8367D_RLDP_ENABLE_OFFSET    0
#define    RTL8367D_RLDP_ENABLE_MASK    0x1

#define    RTL8367D_REG_RLDP_CTRL1    0x18e1
#define    RTL8367D_RLDP_RETRY_COUNT_LOOPSTATE_OFFSET    8
#define    RTL8367D_RLDP_RETRY_COUNT_LOOPSTATE_MASK    0xFF00
#define    RTL8367D_RLDP_RETRY_COUNT_CHKSTATE_OFFSET    0
#define    RTL8367D_RLDP_RETRY_COUNT_CHKSTATE_MASK    0xFF

#define    RTL8367D_REG_RLDP_CTRL2    0x18e2

#define    RTL8367D_REG_RLDP_CTRL3    0x18e3

#define    RTL8367D_REG_RLDP_CTRL4    0x18e4
#define    RTL8367D_RLDP_CTRL4_OFFSET    0
#define    RTL8367D_RLDP_CTRL4_MASK    0xFF

#define    RTL8367D_REG_RLDP_RAND_NUM0    0x18e5

#define    RTL8367D_REG_RLDP_RAND_NUM1    0x18e6

#define    RTL8367D_REG_RLDP_RAND_NUM2    0x18e7

#define    RTL8367D_REG_RLDP_MAGIC_NUM0    0x18e8

#define    RTL8367D_REG_RLDP_MAGIC_NUM1    0x18e9

#define    RTL8367D_REG_RLDP_MAGIC_NUM2    0x18ea

#define    RTL8367D_REG_RLDP_LOOPED_INDICATOR    0x18eb
#define    RTL8367D_RLDP_LOOPED_INDICATOR_OFFSET    0
#define    RTL8367D_RLDP_LOOPED_INDICATOR_MASK    0xFF

#define    RTL8367D_REG_RLDP_LOOP_PORT_REG0    0x18ec
#define    RTL8367D_RLDP_LOOP_PORT_01_OFFSET    8
#define    RTL8367D_RLDP_LOOP_PORT_01_MASK    0x700
#define    RTL8367D_RLDP_LOOP_PORT_00_OFFSET    0
#define    RTL8367D_RLDP_LOOP_PORT_00_MASK    0x7

#define    RTL8367D_REG_RLDP_LOOP_PORT_REG1    0x18ed
#define    RTL8367D_RLDP_LOOP_PORT_03_OFFSET    8
#define    RTL8367D_RLDP_LOOP_PORT_03_MASK    0x700
#define    RTL8367D_RLDP_LOOP_PORT_02_OFFSET    0
#define    RTL8367D_RLDP_LOOP_PORT_02_MASK    0x7

#define    RTL8367D_REG_RLDP_LOOP_PORT_REG2    0x18ee
#define    RTL8367D_RLDP_LOOP_PORT_05_OFFSET    8
#define    RTL8367D_RLDP_LOOP_PORT_05_MASK    0x700
#define    RTL8367D_RLDP_LOOP_PORT_04_OFFSET    0
#define    RTL8367D_RLDP_LOOP_PORT_04_MASK    0x7

#define    RTL8367D_REG_RLDP_LOOP_PORT_REG3    0x18ef
#define    RTL8367D_RLDP_LOOP_PORT_07_OFFSET    8
#define    RTL8367D_RLDP_LOOP_PORT_07_MASK    0x700
#define    RTL8367D_RLDP_LOOP_PORT_06_OFFSET    0
#define    RTL8367D_RLDP_LOOP_PORT_06_MASK    0x7

#define    RTL8367D_REG_RLDP_RELEASED_INDICATOR    0x18f0
#define    RTL8367D_RLDP_RELEASED_INDICATOR_OFFSET    0
#define    RTL8367D_RLDP_RELEASED_INDICATOR_MASK    0xFF

#define    RTL8367D_REG_RLDP_LOOPSTATUS_INDICATOR    0x18f1
#define    RTL8367D_RLDP_LOOPSTATUS_INDICATOR_OFFSET    0
#define    RTL8367D_RLDP_LOOPSTATUS_INDICATOR_MASK    0xFF

/* (16'h1900)EEE_EEEP_reg */

#define    RTL8367D_REG_REG_MULTIWAKE    0x1920
#define    RTL8367D_MULTIWAKE_TIME_UNIT_OFFSET    6
#define    RTL8367D_MULTIWAKE_TIME_UNIT_MASK    0xC0
#define    RTL8367D_MULTIWAKE_PORTS_OFFSET    3
#define    RTL8367D_MULTIWAKE_PORTS_MASK    0x38
#define    RTL8367D_MULTIWAKE_INTLV_OFFSET    1
#define    RTL8367D_MULTIWAKE_INTLV_MASK    0x6
#define    RTL8367D_MULTIWAKE_EN_OFFSET    0
#define    RTL8367D_MULTIWAKE_EN_MASK    0x1

#define    RTL8367D_REG_REG_EEE_MISC    0x1921
#define    RTL8367D_EEE_WAIT_RX_INACTIVE_2P5G_OFFSET    7
#define    RTL8367D_EEE_WAIT_RX_INACTIVE_2P5G_MASK    0x80
#define    RTL8367D_EEE_WAIT_RX_INACTIVE_GE_OFFSET    6
#define    RTL8367D_EEE_WAIT_RX_INACTIVE_GE_MASK    0x40
#define    RTL8367D_EEE_WAIT_RX_INACTIVE_GELITE_OFFSET    5
#define    RTL8367D_EEE_WAIT_RX_INACTIVE_GELITE_MASK    0x20
#define    RTL8367D_EEE_EN_FC_EFCT_OFFSET    4
#define    RTL8367D_EEE_EN_FC_EFCT_MASK    0x10
#define    RTL8367D_EEE_REF_RXLPI_OFFSET    3
#define    RTL8367D_EEE_REF_RXLPI_MASK    0x8
#define    RTL8367D_EEE_LINK_UP_DELAY_OFFSET    1
#define    RTL8367D_EEE_LINK_UP_DELAY_MASK    0x6
#define    RTL8367D_EEE_TX_WAKE_SEL_OFFSET    0
#define    RTL8367D_EEE_TX_WAKE_SEL_MASK    0x1

#define    RTL8367D_REG_REG_EEE_TX_LPI_MINIPG_GELITE    0x1922

#define    RTL8367D_REG_REG_EEE_TX_LPI_MINIPG_FE    0x1923

#define    RTL8367D_REG_REG_EEE_TX_LPI_MINIPG_2P5G    0x1924

#define    RTL8367D_REG_REG_EEE_TX_LPI_MINIPG_GE    0x1925

#define    RTL8367D_REG_REG_EEE_WAIT_RX_INACTIVE_TIMER_2P5G    0x1926
#define    RTL8367D_REG_EEE_WAIT_RX_INACTIVE_TIMER_2P5G_OFFSET    0
#define    RTL8367D_REG_EEE_WAIT_RX_INACTIVE_TIMER_2P5G_MASK    0xFF

#define    RTL8367D_REG_REG_EEE_WAIT_RX_INACTIVE_TIMER    0x1927
#define    RTL8367D_EEE_WAIT_RX_INACTIVE_TIMER_GE_OFFSET    8
#define    RTL8367D_EEE_WAIT_RX_INACTIVE_TIMER_GE_MASK    0xFF00
#define    RTL8367D_EEE_WAIT_RX_INACTIVE_TIMER_GELITE_OFFSET    0
#define    RTL8367D_EEE_WAIT_RX_INACTIVE_TIMER_GELITE_MASK    0xFF

#define    RTL8367D_REG_REG_EEE_LOW_Q_TX_DELAY_FE    0x1928
#define    RTL8367D_REG_EEE_LOW_Q_TX_DELAY_FE_OFFSET    0
#define    RTL8367D_REG_EEE_LOW_Q_TX_DELAY_FE_MASK    0xFFF

#define    RTL8367D_REG_REG_EEE_TX_WAKE_TIMER_FE    0x1929
#define    RTL8367D_REG_EEE_TX_WAKE_TIMER_FE_OFFSET    0
#define    RTL8367D_REG_EEE_TX_WAKE_TIMER_FE_MASK    0xFF

#define    RTL8367D_REG_REG_EEE_LOW_Q_TX_DELAY_GELITE    0x192a
#define    RTL8367D_REG_EEE_LOW_Q_TX_DELAY_GELITE_OFFSET    0
#define    RTL8367D_REG_EEE_LOW_Q_TX_DELAY_GELITE_MASK    0xFFF

#define    RTL8367D_REG_REG_EEE_TX_WAKE_TIMER_GELITE    0x192b
#define    RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_GELITE_OFFSET    8
#define    RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_GELITE_MASK    0xFF00
#define    RTL8367D_EEE_TX_WAKE_TIMER_GELITE_OFFSET    0
#define    RTL8367D_EEE_TX_WAKE_TIMER_GELITE_MASK    0xFF

#define    RTL8367D_REG_REG_EEE_LOW_Q_TX_DELAY_GE    0x192c
#define    RTL8367D_REG_EEE_LOW_Q_TX_DELAY_GE_OFFSET    0
#define    RTL8367D_REG_EEE_LOW_Q_TX_DELAY_GE_MASK    0xFFF

#define    RTL8367D_REG_REG_EEE_TX_WAKE_TIMER_GE    0x192d
#define    RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_GE_OFFSET    8
#define    RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_GE_MASK    0xFF00
#define    RTL8367D_EEE_TX_WAKE_TIMER_GE_OFFSET    0
#define    RTL8367D_EEE_TX_WAKE_TIMER_GE_MASK    0xFF

#define    RTL8367D_REG_REG_EEE_LOW_Q_TX_DELAY_2P5G    0x192e
#define    RTL8367D_REG_EEE_LOW_Q_TX_DELAY_2P5G_OFFSET    0
#define    RTL8367D_REG_EEE_LOW_Q_TX_DELAY_2P5G_MASK    0xFFF

#define    RTL8367D_REG_REG_EEE_TX_WAKE_TIMER_2P5G    0x192f
#define    RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_2P5G_OFFSET    8
#define    RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_2P5G_MASK    0xFF00
#define    RTL8367D_EEE_TX_WAKE_TIMER_2P5G_OFFSET    0
#define    RTL8367D_EEE_TX_WAKE_TIMER_2P5G_MASK    0xFF

/* (16'h1b00)LED */

#define    RTL8367D_REG_LED_SYS_CONFIG    0x1b00
#define    RTL8367D_LED_SYS_CONFIG_DUMMY_15_OFFSET    15
#define    RTL8367D_LED_SYS_CONFIG_DUMMY_15_MASK    0x8000
#define    RTL8367D_LED_SERIAL_OUT_MODE_OFFSET    14
#define    RTL8367D_LED_SERIAL_OUT_MODE_MASK    0x4000
#define    RTL8367D_LED_EEE_LPI_MODE_OFFSET    13
#define    RTL8367D_LED_EEE_LPI_MODE_MASK    0x2000
#define    RTL8367D_LED_EEE_LPI_EN_OFFSET    12
#define    RTL8367D_LED_EEE_LPI_EN_MASK    0x1000
#define    RTL8367D_LED_EEE_LPI_10_OFFSET    11
#define    RTL8367D_LED_EEE_LPI_10_MASK    0x800
#define    RTL8367D_LED_EEE_CAP_10_OFFSET    10
#define    RTL8367D_LED_EEE_CAP_10_MASK    0x400
#define    RTL8367D_LED_LPI_SEL_OFFSET    8
#define    RTL8367D_LED_LPI_SEL_MASK    0x300
#define    RTL8367D_SERI_LED_ACT_LOW_OFFSET    7
#define    RTL8367D_SERI_LED_ACT_LOW_MASK    0x80
#define    RTL8367D_LED_POWERON_2_OFFSET    6
#define    RTL8367D_LED_POWERON_2_MASK    0x40
#define    RTL8367D_LED_POWERON_1_OFFSET    5
#define    RTL8367D_LED_POWERON_1_MASK    0x20
#define    RTL8367D_LED_POWERON_0_OFFSET    4
#define    RTL8367D_LED_POWERON_0_MASK    0x10
#define    RTL8367D_LED_IO_DISABLE_OFFSET    3
#define    RTL8367D_LED_IO_DISABLE_MASK    0x8
#define    RTL8367D_DUMMY_2_OFFSET    2
#define    RTL8367D_DUMMY_2_MASK    0x4
#define    RTL8367D_LED_SERIAL2_OFFSET    1
#define    RTL8367D_LED_SERIAL2_MASK    0x2
#define    RTL8367D_LED_SELECT_OFFSET    0
#define    RTL8367D_LED_SELECT_MASK    0x1

#define    RTL8367D_REG_LED_SYS_CONFIG2    0x1b01
#define    RTL8367D_LED_SYS_CONFIG2_DUMMY_OFFSET    2
#define    RTL8367D_LED_SYS_CONFIG2_DUMMY_MASK    0xFFFC
#define    RTL8367D_GATE_LPTD_BYPASS_OFFSET    1
#define    RTL8367D_GATE_LPTD_BYPASS_MASK    0x2
#define    RTL8367D_LED_SPD_MODE_OFFSET    0
#define    RTL8367D_LED_SPD_MODE_MASK    0x1

#define    RTL8367D_REG_LED_MODE    0x1b02
#define    RTL8367D_DLINK_TIME_OFFSET    15
#define    RTL8367D_DLINK_TIME_MASK    0x8000
#define    RTL8367D_LED_BUZZ_DUTY_OFFSET    14
#define    RTL8367D_LED_BUZZ_DUTY_MASK    0x4000
#define    RTL8367D_BUZZER_RATE_OFFSET    12
#define    RTL8367D_BUZZER_RATE_MASK    0x3000
#define    RTL8367D_LOOP_DETECT_MODE_OFFSET    11
#define    RTL8367D_LOOP_DETECT_MODE_MASK    0x800
#define    RTL8367D_SEL_PWRON_TIME_OFFSET    9
#define    RTL8367D_SEL_PWRON_TIME_MASK    0x600
#define    RTL8367D_EN_DLINK_LED_OFFSET    8
#define    RTL8367D_EN_DLINK_LED_MASK    0x100
#define    RTL8367D_LOOP_DETECT_RATE_OFFSET    6
#define    RTL8367D_LOOP_DETECT_RATE_MASK    0xC0
#define    RTL8367D_FORCE_RATE_OFFSET    4
#define    RTL8367D_FORCE_RATE_MASK    0x30
#define    RTL8367D_SEL_LEDRATE_OFFSET    1
#define    RTL8367D_SEL_LEDRATE_MASK    0xE
#define    RTL8367D_SPEED_UP_OFFSET    0
#define    RTL8367D_SPEED_UP_MASK    0x1

#define    RTL8367D_REG_LED_CONFIGURATION    0x1b03
#define    RTL8367D_LED_CONFIGURATION_DUMMY_OFFSET    15
#define    RTL8367D_LED_CONFIGURATION_DUMMY_MASK    0x8000
#define    RTL8367D_LED_CONFIG_SEL_OFFSET    14
#define    RTL8367D_LED_CONFIG_SEL_MASK    0x4000
#define    RTL8367D_DATA_LED_OFFSET    12
#define    RTL8367D_DATA_LED_MASK    0x3000
#define    RTL8367D_LED2_CFG_OFFSET    8
#define    RTL8367D_LED2_CFG_MASK    0xF00
#define    RTL8367D_LED1_CFG_OFFSET    4
#define    RTL8367D_LED1_CFG_MASK    0xF0
#define    RTL8367D_LED0_CFG_OFFSET    0
#define    RTL8367D_LED0_CFG_MASK    0xF

#define    RTL8367D_REG_RTCT_RESULTS_CFG    0x1b04
#define    RTL8367D_RTCT_2PAIR_FTT_OFFSET    15
#define    RTL8367D_RTCT_2PAIR_FTT_MASK    0x8000
#define    RTL8367D_RTCT_2PAIR_MODE_OFFSET    14
#define    RTL8367D_RTCT_2PAIR_MODE_MASK    0x4000
#define    RTL8367D_BLINK_EN_OFFSET    13
#define    RTL8367D_BLINK_EN_MASK    0x2000
#define    RTL8367D_TIMEOUT_OFFSET    12
#define    RTL8367D_TIMEOUT_MASK    0x1000
#define    RTL8367D_EN_CD_SAME_SHORT_OFFSET    11
#define    RTL8367D_EN_CD_SAME_SHORT_MASK    0x800
#define    RTL8367D_EN_CD_SAME_OPEN_OFFSET    10
#define    RTL8367D_EN_CD_SAME_OPEN_MASK    0x400
#define    RTL8367D_EN_CD_SAME_MISMATCH_OFFSET    9
#define    RTL8367D_EN_CD_SAME_MISMATCH_MASK    0x200
#define    RTL8367D_EN_CD_SAME_LINEDRIVER_OFFSET    8
#define    RTL8367D_EN_CD_SAME_LINEDRIVER_MASK    0x100
#define    RTL8367D_EN_CD_SHORT_OFFSET    7
#define    RTL8367D_EN_CD_SHORT_MASK    0x80
#define    RTL8367D_EN_AB_SHORT_OFFSET    6
#define    RTL8367D_EN_AB_SHORT_MASK    0x40
#define    RTL8367D_EN_CD_OPEN_OFFSET    5
#define    RTL8367D_EN_CD_OPEN_MASK    0x20
#define    RTL8367D_EN_AB_OPEN_OFFSET    4
#define    RTL8367D_EN_AB_OPEN_MASK    0x10
#define    RTL8367D_EN_CD_MISMATCH_OFFSET    3
#define    RTL8367D_EN_CD_MISMATCH_MASK    0x8
#define    RTL8367D_EN_AB_MISMATCH_OFFSET    2
#define    RTL8367D_EN_AB_MISMATCH_MASK    0x4
#define    RTL8367D_EN_CD_LINEDRIVER_OFFSET    1
#define    RTL8367D_EN_CD_LINEDRIVER_MASK    0x2
#define    RTL8367D_EN_AB_LINEDRIVER_OFFSET    0
#define    RTL8367D_EN_AB_LINEDRIVER_MASK    0x1

#define    RTL8367D_REG_RTCT_LED    0x1b05
#define    RTL8367D_RTCT_LED_DUMMY_OFFSET    12
#define    RTL8367D_RTCT_LED_DUMMY_MASK    0xF000
#define    RTL8367D_RTCT_LED2_OFFSET    8
#define    RTL8367D_RTCT_LED2_MASK    0xF00
#define    RTL8367D_RTCT_LED1_OFFSET    4
#define    RTL8367D_RTCT_LED1_MASK    0xF0
#define    RTL8367D_RTCT_LED0_OFFSET    0
#define    RTL8367D_RTCT_LED0_MASK    0xF

#define    RTL8367D_REG_CPU_FORCE_LED_CFG    0x1b07
#define    RTL8367D_CPU_FORCE_LED_CFG_DUMMY_OFFSET    8
#define    RTL8367D_CPU_FORCE_LED_CFG_DUMMY_MASK    0xFF00
#define    RTL8367D_LED_FORCE_MODE_OFFSET    2
#define    RTL8367D_LED_FORCE_MODE_MASK    0xFC
#define    RTL8367D_FORCE_MODE_OFFSET    0
#define    RTL8367D_FORCE_MODE_MASK    0x3

#define    RTL8367D_REG_CPU_FORCE_LED0_CFG0    0x1b08
#define    RTL8367D_PORT7_LED0_MODE_OFFSET    14
#define    RTL8367D_PORT7_LED0_MODE_MASK    0xC000
#define    RTL8367D_PORT6_LED0_MODE_OFFSET    12
#define    RTL8367D_PORT6_LED0_MODE_MASK    0x3000
#define    RTL8367D_PORT5_LED0_MODE_OFFSET    10
#define    RTL8367D_PORT5_LED0_MODE_MASK    0xC00
#define    RTL8367D_PORT4_LED0_MODE_OFFSET    8
#define    RTL8367D_PORT4_LED0_MODE_MASK    0x300
#define    RTL8367D_PORT3_LED0_MODE_OFFSET    6
#define    RTL8367D_PORT3_LED0_MODE_MASK    0xC0
#define    RTL8367D_PORT2_LED0_MODE_OFFSET    4
#define    RTL8367D_PORT2_LED0_MODE_MASK    0x30
#define    RTL8367D_PORT1_LED0_MODE_OFFSET    2
#define    RTL8367D_PORT1_LED0_MODE_MASK    0xC
#define    RTL8367D_PORT0_LED0_MODE_OFFSET    0
#define    RTL8367D_PORT0_LED0_MODE_MASK    0x3

#define    RTL8367D_REG_CPU_FORCE_LED1_CFG0    0x1b0a
#define    RTL8367D_PORT7_LED1_MODE_OFFSET    14
#define    RTL8367D_PORT7_LED1_MODE_MASK    0xC000
#define    RTL8367D_PORT6_LED1_MODE_OFFSET    12
#define    RTL8367D_PORT6_LED1_MODE_MASK    0x3000
#define    RTL8367D_PORT5_LED1_MODE_OFFSET    10
#define    RTL8367D_PORT5_LED1_MODE_MASK    0xC00
#define    RTL8367D_PORT4_LED1_MODE_OFFSET    8
#define    RTL8367D_PORT4_LED1_MODE_MASK    0x300
#define    RTL8367D_PORT3_LED1_MODE_OFFSET    6
#define    RTL8367D_PORT3_LED1_MODE_MASK    0xC0
#define    RTL8367D_PORT2_LED1_MODE_OFFSET    4
#define    RTL8367D_PORT2_LED1_MODE_MASK    0x30
#define    RTL8367D_PORT1_LED1_MODE_OFFSET    2
#define    RTL8367D_PORT1_LED1_MODE_MASK    0xC
#define    RTL8367D_PORT0_LED1_MODE_OFFSET    0
#define    RTL8367D_PORT0_LED1_MODE_MASK    0x3

#define    RTL8367D_REG_CPU_FORCE_LED2_CFG0    0x1b0c
#define    RTL8367D_PORT7_LED2_MODE_OFFSET    14
#define    RTL8367D_PORT7_LED2_MODE_MASK    0xC000
#define    RTL8367D_PORT6_LED2_MODE_OFFSET    12
#define    RTL8367D_PORT6_LED2_MODE_MASK    0x3000
#define    RTL8367D_PORT5_LED2_MODE_OFFSET    10
#define    RTL8367D_PORT5_LED2_MODE_MASK    0xC00
#define    RTL8367D_PORT4_LED2_MODE_OFFSET    8
#define    RTL8367D_PORT4_LED2_MODE_MASK    0x300
#define    RTL8367D_PORT3_LED2_MODE_OFFSET    6
#define    RTL8367D_PORT3_LED2_MODE_MASK    0xC0
#define    RTL8367D_PORT2_LED2_MODE_OFFSET    4
#define    RTL8367D_PORT2_LED2_MODE_MASK    0x30
#define    RTL8367D_PORT1_LED2_MODE_OFFSET    2
#define    RTL8367D_PORT1_LED2_MODE_MASK    0xC
#define    RTL8367D_PORT0_LED2_MODE_OFFSET    0
#define    RTL8367D_PORT0_LED2_MODE_MASK    0x3

#define    RTL8367D_REG_LED_ACTIVE_LOW_CFG0    0x1b0e
#define    RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_15_OFFSET    15
#define    RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_15_MASK    0x8000
#define    RTL8367D_PORT3_LED_ACTIVE_LOW_OFFSET    12
#define    RTL8367D_PORT3_LED_ACTIVE_LOW_MASK    0x7000
#define    RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_11_OFFSET    11
#define    RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_11_MASK    0x800
#define    RTL8367D_PORT2_LED_ACTIVE_LOW_OFFSET    8
#define    RTL8367D_PORT2_LED_ACTIVE_LOW_MASK    0x700
#define    RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_7_OFFSET    7
#define    RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_7_MASK    0x80
#define    RTL8367D_PORT1_LED_ACTIVE_LOW_OFFSET    4
#define    RTL8367D_PORT1_LED_ACTIVE_LOW_MASK    0x70
#define    RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_3_OFFSET    3
#define    RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_3_MASK    0x8
#define    RTL8367D_PORT0_LED_ACTIVE_LOW_OFFSET    0
#define    RTL8367D_PORT0_LED_ACTIVE_LOW_MASK    0x7

#define    RTL8367D_REG_LED_ACTIVE_LOW_CFG1    0x1b0f
#define    RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_15_OFFSET    15
#define    RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_15_MASK    0x8000
#define    RTL8367D_PORT7_LED_ACTIVE_LOW_OFFSET    12
#define    RTL8367D_PORT7_LED_ACTIVE_LOW_MASK    0x7000
#define    RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_11_OFFSET    11
#define    RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_11_MASK    0x800
#define    RTL8367D_PORT6_LED_ACTIVE_LOW_OFFSET    8
#define    RTL8367D_PORT6_LED_ACTIVE_LOW_MASK    0x700
#define    RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_7_OFFSET    7
#define    RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_7_MASK    0x80
#define    RTL8367D_PORT5_LED_ACTIVE_LOW_OFFSET    4
#define    RTL8367D_PORT5_LED_ACTIVE_LOW_MASK    0x70
#define    RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_3_OFFSET    3
#define    RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_3_MASK    0x8
#define    RTL8367D_PORT4_LED_ACTIVE_LOW_OFFSET    0
#define    RTL8367D_PORT4_LED_ACTIVE_LOW_MASK    0x7

#define    RTL8367D_REG_SEL_RTCT_PARA    0x1b21
#define    RTL8367D_DO_RTCT_COMMAND_OFFSET    15
#define    RTL8367D_DO_RTCT_COMMAND_MASK    0x8000
#define    RTL8367D_SEL_RTCT_PARA_DUMMY_OFFSET    12
#define    RTL8367D_SEL_RTCT_PARA_DUMMY_MASK    0x7000
#define    RTL8367D_SEL_RTCT_RLSTLED_TIME_OFFSET    10
#define    RTL8367D_SEL_RTCT_RLSTLED_TIME_MASK    0xC00
#define    RTL8367D_SEL_RTCT_TEST_LED_TIME_OFFSET    8
#define    RTL8367D_SEL_RTCT_TEST_LED_TIME_MASK    0x300
#define    RTL8367D_EN_SCAN_RTCT_OFFSET    7
#define    RTL8367D_EN_SCAN_RTCT_MASK    0x80
#define    RTL8367D_EN_RTCT_TIMOUT_OFFSET    6
#define    RTL8367D_EN_RTCT_TIMOUT_MASK    0x40
#define    RTL8367D_EN_ALL_RTCT_OFFSET    5
#define    RTL8367D_EN_ALL_RTCT_MASK    0x20
#define    RTL8367D_SEL_RTCT_PLE_WID_OFFSET    0
#define    RTL8367D_SEL_RTCT_PLE_WID_MASK    0x1F

#define    RTL8367D_REG_RTCT_ENABLE    0x1b22
#define    RTL8367D_RTCT_ENABLE_DUMMY_OFFSET    5
#define    RTL8367D_RTCT_ENABLE_DUMMY_MASK    0xFFE0
#define    RTL8367D_RTCT_ENABLE_PORT_MASK_OFFSET    0
#define    RTL8367D_RTCT_ENABLE_PORT_MASK_MASK    0x1F

#define    RTL8367D_REG_RTCT_TIMEOUT    0x1b23

#define    RTL8367D_REG_PARA_LED_IO_EN1    0x1b24
#define    RTL8367D_DUMMY_15_13_OFFSET    13
#define    RTL8367D_DUMMY_15_13_MASK    0xE000
#define    RTL8367D_LED1_PARA_P04_00_OFFSET    8
#define    RTL8367D_LED1_PARA_P04_00_MASK    0x1F00
#define    RTL8367D_DUMMY_7_5_OFFSET    5
#define    RTL8367D_DUMMY_7_5_MASK    0xE0
#define    RTL8367D_LED0_PARA_P04_00_OFFSET    0
#define    RTL8367D_LED0_PARA_P04_00_MASK    0x1F

#define    RTL8367D_REG_PARA_LED_IO_EN2    0x1b25
#define    RTL8367D_DUMMY_15_5_OFFSET    5
#define    RTL8367D_DUMMY_15_5_MASK    0xFFE0
#define    RTL8367D_LED2_PARA_P04_00_OFFSET    0
#define    RTL8367D_LED2_PARA_P04_00_MASK    0x1F

#define    RTL8367D_REG_SCAN0_LED_IO_EN    0x1b26
#define    RTL8367D_SCAN0_LED_IO_EN_DUMMY_OFFSET    3
#define    RTL8367D_SCAN0_LED_IO_EN_DUMMY_MASK    0xFFF8
#define    RTL8367D_LED_LOOP_DET_BUZZER_EN_OFFSET    2
#define    RTL8367D_LED_LOOP_DET_BUZZER_EN_MASK    0x4
#define    RTL8367D_LED_SERI_DATA_EN_OFFSET    1
#define    RTL8367D_LED_SERI_DATA_EN_MASK    0x2
#define    RTL8367D_LED_SERI_CLK_EN_OFFSET    0
#define    RTL8367D_LED_SERI_CLK_EN_MASK    0x1

#define    RTL8367D_REG_LPI_LED_OPT1    0x1b28
#define    RTL8367D_LPI_TAG4_OFFSET    12
#define    RTL8367D_LPI_TAG4_MASK    0xF000
#define    RTL8367D_LPI_TAG3_OFFSET    8
#define    RTL8367D_LPI_TAG3_MASK    0xF00
#define    RTL8367D_LPI_TAG2_OFFSET    4
#define    RTL8367D_LPI_TAG2_MASK    0xF0
#define    RTL8367D_LPI_TAG1_OFFSET    0
#define    RTL8367D_LPI_TAG1_MASK    0xF

#define    RTL8367D_REG_LPI_LED_OPT2    0x1b29
#define    RTL8367D_LPI_LED_OPT2_DUMMY_OFFSET    15
#define    RTL8367D_LPI_LED_OPT2_DUMMY_MASK    0x8000
#define    RTL8367D_LPI_LED2_WEAK_OFFSET    14
#define    RTL8367D_LPI_LED2_WEAK_MASK    0x4000
#define    RTL8367D_LPI_LED1_WEAK_OFFSET    13
#define    RTL8367D_LPI_LED1_WEAK_MASK    0x2000
#define    RTL8367D_LPI_LED0_WEAK_OFFSET    12
#define    RTL8367D_LPI_LED0_WEAK_MASK    0x1000
#define    RTL8367D_LPI_LED2_OFFSET    11
#define    RTL8367D_LPI_LED2_MASK    0x800
#define    RTL8367D_LPI_LED1_OFFSET    10
#define    RTL8367D_LPI_LED1_MASK    0x400
#define    RTL8367D_LPI_LED0_OFFSET    9
#define    RTL8367D_LPI_LED0_MASK    0x200
#define    RTL8367D_LPI_TAG8_OFFSET    8
#define    RTL8367D_LPI_TAG8_MASK    0x100
#define    RTL8367D_LPI_TAG7_OFFSET    6
#define    RTL8367D_LPI_TAG7_MASK    0xC0
#define    RTL8367D_LPI_TAG6_OFFSET    4
#define    RTL8367D_LPI_TAG6_MASK    0x30
#define    RTL8367D_LPI_TAG5_OFFSET    0
#define    RTL8367D_LPI_TAG5_MASK    0xF

#define    RTL8367D_REG_LPI_LED_OPT3    0x1b2a
#define    RTL8367D_LPI_LED_OPT3_DUMMY_OFFSET    3
#define    RTL8367D_LPI_LED_OPT3_DUMMY_MASK    0xFFF8
#define    RTL8367D_RESTORE_LED_RATE_SEL_OFFSET    1
#define    RTL8367D_RESTORE_LED_RATE_SEL_MASK    0x6
#define    RTL8367D_RESTORE_LED_SEL_OFFSET    0
#define    RTL8367D_RESTORE_LED_SEL_MASK    0x1

#define    RTL8367D_REG_P0_LED_MUX    0x1b2b
#define    RTL8367D_P0_LED_MUX_DUMMY_OFFSET    15
#define    RTL8367D_P0_LED_MUX_DUMMY_MASK    0x8000
#define    RTL8367D_CFG_P0_LED2_MUX_OFFSET    10
#define    RTL8367D_CFG_P0_LED2_MUX_MASK    0x7C00
#define    RTL8367D_CFG_P0_LED1_MUX_OFFSET    5
#define    RTL8367D_CFG_P0_LED1_MUX_MASK    0x3E0
#define    RTL8367D_CFG_P0_LED0_MUX_OFFSET    0
#define    RTL8367D_CFG_P0_LED0_MUX_MASK    0x1F

#define    RTL8367D_REG_P1_LED_MUX    0x1b2c
#define    RTL8367D_P1_LED_MUX_DUMMY_OFFSET    15
#define    RTL8367D_P1_LED_MUX_DUMMY_MASK    0x8000
#define    RTL8367D_CFG_P1_LED2_MUX_OFFSET    10
#define    RTL8367D_CFG_P1_LED2_MUX_MASK    0x7C00
#define    RTL8367D_CFG_P1_LED1_MUX_OFFSET    5
#define    RTL8367D_CFG_P1_LED1_MUX_MASK    0x3E0
#define    RTL8367D_CFG_P1_LED0_MUX_OFFSET    0
#define    RTL8367D_CFG_P1_LED0_MUX_MASK    0x1F

#define    RTL8367D_REG_P2_LED_MUX    0x1b2d
#define    RTL8367D_P2_LED_MUX_DUMMY_OFFSET    15
#define    RTL8367D_P2_LED_MUX_DUMMY_MASK    0x8000
#define    RTL8367D_CFG_P2_LED2_MUX_OFFSET    10
#define    RTL8367D_CFG_P2_LED2_MUX_MASK    0x7C00
#define    RTL8367D_CFG_P2_LED1_MUX_OFFSET    5
#define    RTL8367D_CFG_P2_LED1_MUX_MASK    0x3E0
#define    RTL8367D_CFG_P2_LED0_MUX_OFFSET    0
#define    RTL8367D_CFG_P2_LED0_MUX_MASK    0x1F

#define    RTL8367D_REG_P3_LED_MUX    0x1b2e
#define    RTL8367D_P3_LED_MUX_DUMMY_OFFSET    15
#define    RTL8367D_P3_LED_MUX_DUMMY_MASK    0x8000
#define    RTL8367D_CFG_P3_LED2_MUX_OFFSET    10
#define    RTL8367D_CFG_P3_LED2_MUX_MASK    0x7C00
#define    RTL8367D_CFG_P3_LED1_MUX_OFFSET    5
#define    RTL8367D_CFG_P3_LED1_MUX_MASK    0x3E0
#define    RTL8367D_CFG_P3_LED0_MUX_OFFSET    0
#define    RTL8367D_CFG_P3_LED0_MUX_MASK    0x1F

#define    RTL8367D_REG_P4_LED_MUX    0x1b2f
#define    RTL8367D_P4_LED_MUX_DUMMY_OFFSET    15
#define    RTL8367D_P4_LED_MUX_DUMMY_MASK    0x8000
#define    RTL8367D_CFG_P4_LED2_MUX_OFFSET    10
#define    RTL8367D_CFG_P4_LED2_MUX_MASK    0x7C00
#define    RTL8367D_CFG_P4_LED1_MUX_OFFSET    5
#define    RTL8367D_CFG_P4_LED1_MUX_MASK    0x3E0
#define    RTL8367D_CFG_P4_LED0_MUX_OFFSET    0
#define    RTL8367D_CFG_P4_LED0_MUX_MASK    0x1F

#define    RTL8367D_REG_LED0_DATA_CTRL    0x1b30
#define    RTL8367D_LED0_DATA_CTRL_DUMMY_OFFSET    9
#define    RTL8367D_LED0_DATA_CTRL_DUMMY_MASK    0xFE00
#define    RTL8367D_CFG_DATA_LED0_DIS_OFFSET    8
#define    RTL8367D_CFG_DATA_LED0_DIS_MASK    0x100
#define    RTL8367D_CFG_DATA_LED0_SEL_OFFSET    7
#define    RTL8367D_CFG_DATA_LED0_SEL_MASK    0x80
#define    RTL8367D_CFG_DATA_LED0_ACT_OFFSET    5
#define    RTL8367D_CFG_DATA_LED0_ACT_MASK    0x60
#define    RTL8367D_CFG_DATA_LED0_SPD_OFFSET    0
#define    RTL8367D_CFG_DATA_LED0_SPD_MASK    0x1F

#define    RTL8367D_REG_LED1_DATA_CTRL    0x1b31
#define    RTL8367D_LED1_DATA_CTRL_DUMMY_OFFSET    9
#define    RTL8367D_LED1_DATA_CTRL_DUMMY_MASK    0xFE00
#define    RTL8367D_CFG_DATA_LED1_DIS_OFFSET    8
#define    RTL8367D_CFG_DATA_LED1_DIS_MASK    0x100
#define    RTL8367D_CFG_DATA_LED1_SEL_OFFSET    7
#define    RTL8367D_CFG_DATA_LED1_SEL_MASK    0x80
#define    RTL8367D_CFG_DATA_LED1_ACT_OFFSET    5
#define    RTL8367D_CFG_DATA_LED1_ACT_MASK    0x60
#define    RTL8367D_CFG_DATA_LED1_SPD_OFFSET    0
#define    RTL8367D_CFG_DATA_LED1_SPD_MASK    0x1F

#define    RTL8367D_REG_LED2_DATA_CTRL    0x1b32
#define    RTL8367D_LED2_DATA_CTRL_DUMMY_OFFSET    9
#define    RTL8367D_LED2_DATA_CTRL_DUMMY_MASK    0xFE00
#define    RTL8367D_CFG_DATA_LED2_DIS_OFFSET    8
#define    RTL8367D_CFG_DATA_LED2_DIS_MASK    0x100
#define    RTL8367D_CFG_DATA_LED2_SEL_OFFSET    7
#define    RTL8367D_CFG_DATA_LED2_SEL_MASK    0x80
#define    RTL8367D_CFG_DATA_LED2_ACT_OFFSET    5
#define    RTL8367D_CFG_DATA_LED2_ACT_MASK    0x60
#define    RTL8367D_CFG_DATA_LED2_SPD_OFFSET    0
#define    RTL8367D_CFG_DATA_LED2_SPD_MASK    0x1F

/* (16'h1c00)IGMP_EAV */

#define    RTL8367D_REG_IGMP_MLD_CFG0    0x1c00
#define    RTL8367D_IGMP_MLD_PORTISO_LEAKY_OFFSET    15
#define    RTL8367D_IGMP_MLD_PORTISO_LEAKY_MASK    0x8000
#define    RTL8367D_IGMP_MLD_VLAN_LEAKY_OFFSET    14
#define    RTL8367D_IGMP_MLD_VLAN_LEAKY_MASK    0x4000
#define    RTL8367D_IGMP_MLD_DISCARD_STORM_FILTER_OFFSET    13
#define    RTL8367D_IGMP_MLD_DISCARD_STORM_FILTER_MASK    0x2000

#define    RTL8367D_REG_IGMP_PORT0_CONTROL    0x1c05
#define    RTL8367D_IGMP_PORT0_CONTROL_MLDv2_OP_OFFSET    8
#define    RTL8367D_IGMP_PORT0_CONTROL_MLDv2_OP_MASK    0x300
#define    RTL8367D_IGMP_PORT0_CONTROL_MLDv1_OP_OFFSET    6
#define    RTL8367D_IGMP_PORT0_CONTROL_MLDv1_OP_MASK    0xC0
#define    RTL8367D_IGMP_PORT0_CONTROL_IGMPV3_OP_OFFSET    4
#define    RTL8367D_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK    0x30
#define    RTL8367D_IGMP_PORT0_CONTROL_IGMPV2_OP_OFFSET    2
#define    RTL8367D_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK    0xC
#define    RTL8367D_IGMP_PORT0_CONTROL_IGMPV1_OP_OFFSET    0
#define    RTL8367D_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK    0x3

#define    RTL8367D_REG_IGMP_PORT1_CONTROL    0x1c06
#define    RTL8367D_IGMP_PORT1_CONTROL_MLDv2_OP_OFFSET    8
#define    RTL8367D_IGMP_PORT1_CONTROL_MLDv2_OP_MASK    0x300
#define    RTL8367D_IGMP_PORT1_CONTROL_MLDv1_OP_OFFSET    6
#define    RTL8367D_IGMP_PORT1_CONTROL_MLDv1_OP_MASK    0xC0
#define    RTL8367D_IGMP_PORT1_CONTROL_IGMPV3_OP_OFFSET    4
#define    RTL8367D_IGMP_PORT1_CONTROL_IGMPV3_OP_MASK    0x30
#define    RTL8367D_IGMP_PORT1_CONTROL_IGMPV2_OP_OFFSET    2
#define    RTL8367D_IGMP_PORT1_CONTROL_IGMPV2_OP_MASK    0xC
#define    RTL8367D_IGMP_PORT1_CONTROL_IGMPV1_OP_OFFSET    0
#define    RTL8367D_IGMP_PORT1_CONTROL_IGMPV1_OP_MASK    0x3

#define    RTL8367D_REG_IGMP_PORT2_CONTROL    0x1c07
#define    RTL8367D_IGMP_PORT2_CONTROL_MLDv2_OP_OFFSET    8
#define    RTL8367D_IGMP_PORT2_CONTROL_MLDv2_OP_MASK    0x300
#define    RTL8367D_IGMP_PORT2_CONTROL_MLDv1_OP_OFFSET    6
#define    RTL8367D_IGMP_PORT2_CONTROL_MLDv1_OP_MASK    0xC0
#define    RTL8367D_IGMP_PORT2_CONTROL_IGMPV3_OP_OFFSET    4
#define    RTL8367D_IGMP_PORT2_CONTROL_IGMPV3_OP_MASK    0x30
#define    RTL8367D_IGMP_PORT2_CONTROL_IGMPV2_OP_OFFSET    2
#define    RTL8367D_IGMP_PORT2_CONTROL_IGMPV2_OP_MASK    0xC
#define    RTL8367D_IGMP_PORT2_CONTROL_IGMPV1_OP_OFFSET    0
#define    RTL8367D_IGMP_PORT2_CONTROL_IGMPV1_OP_MASK    0x3

#define    RTL8367D_REG_IGMP_PORT3_CONTROL    0x1c08
#define    RTL8367D_IGMP_PORT3_CONTROL_MLDv2_OP_OFFSET    8
#define    RTL8367D_IGMP_PORT3_CONTROL_MLDv2_OP_MASK    0x300
#define    RTL8367D_IGMP_PORT3_CONTROL_MLDv1_OP_OFFSET    6
#define    RTL8367D_IGMP_PORT3_CONTROL_MLDv1_OP_MASK    0xC0
#define    RTL8367D_IGMP_PORT3_CONTROL_IGMPV3_OP_OFFSET    4
#define    RTL8367D_IGMP_PORT3_CONTROL_IGMPV3_OP_MASK    0x30
#define    RTL8367D_IGMP_PORT3_CONTROL_IGMPV2_OP_OFFSET    2
#define    RTL8367D_IGMP_PORT3_CONTROL_IGMPV2_OP_MASK    0xC
#define    RTL8367D_IGMP_PORT3_CONTROL_IGMPV1_OP_OFFSET    0
#define    RTL8367D_IGMP_PORT3_CONTROL_IGMPV1_OP_MASK    0x3

#define    RTL8367D_REG_IGMP_PORT4_CONTROL    0x1c09
#define    RTL8367D_IGMP_PORT4_CONTROL_MLDv2_OP_OFFSET    8
#define    RTL8367D_IGMP_PORT4_CONTROL_MLDv2_OP_MASK    0x300
#define    RTL8367D_IGMP_PORT4_CONTROL_MLDv1_OP_OFFSET    6
#define    RTL8367D_IGMP_PORT4_CONTROL_MLDv1_OP_MASK    0xC0
#define    RTL8367D_IGMP_PORT4_CONTROL_IGMPV3_OP_OFFSET    4
#define    RTL8367D_IGMP_PORT4_CONTROL_IGMPV3_OP_MASK    0x30
#define    RTL8367D_IGMP_PORT4_CONTROL_IGMPV2_OP_OFFSET    2
#define    RTL8367D_IGMP_PORT4_CONTROL_IGMPV2_OP_MASK    0xC
#define    RTL8367D_IGMP_PORT4_CONTROL_IGMPV1_OP_OFFSET    0
#define    RTL8367D_IGMP_PORT4_CONTROL_IGMPV1_OP_MASK    0x3

#define    RTL8367D_REG_IGMP_PORT5_CONTROL    0x1c0a
#define    RTL8367D_IGMP_PORT5_CONTROL_MLDv2_OP_OFFSET    8
#define    RTL8367D_IGMP_PORT5_CONTROL_MLDv2_OP_MASK    0x300
#define    RTL8367D_IGMP_PORT5_CONTROL_MLDv1_OP_OFFSET    6
#define    RTL8367D_IGMP_PORT5_CONTROL_MLDv1_OP_MASK    0xC0
#define    RTL8367D_IGMP_PORT5_CONTROL_IGMPV3_OP_OFFSET    4
#define    RTL8367D_IGMP_PORT5_CONTROL_IGMPV3_OP_MASK    0x30
#define    RTL8367D_IGMP_PORT5_CONTROL_IGMPV2_OP_OFFSET    2
#define    RTL8367D_IGMP_PORT5_CONTROL_IGMPV2_OP_MASK    0xC
#define    RTL8367D_IGMP_PORT5_CONTROL_IGMPV1_OP_OFFSET    0
#define    RTL8367D_IGMP_PORT5_CONTROL_IGMPV1_OP_MASK    0x3

#define    RTL8367D_REG_IGMP_PORT6_CONTROL    0x1c0b
#define    RTL8367D_IGMP_PORT6_CONTROL_MLDv2_OP_OFFSET    8
#define    RTL8367D_IGMP_PORT6_CONTROL_MLDv2_OP_MASK    0x300
#define    RTL8367D_IGMP_PORT6_CONTROL_MLDv1_OP_OFFSET    6
#define    RTL8367D_IGMP_PORT6_CONTROL_MLDv1_OP_MASK    0xC0
#define    RTL8367D_IGMP_PORT6_CONTROL_IGMPV3_OP_OFFSET    4
#define    RTL8367D_IGMP_PORT6_CONTROL_IGMPV3_OP_MASK    0x30
#define    RTL8367D_IGMP_PORT6_CONTROL_IGMPV2_OP_OFFSET    2
#define    RTL8367D_IGMP_PORT6_CONTROL_IGMPV2_OP_MASK    0xC
#define    RTL8367D_IGMP_PORT6_CONTROL_IGMPV1_OP_OFFSET    0
#define    RTL8367D_IGMP_PORT6_CONTROL_IGMPV1_OP_MASK    0x3

#define    RTL8367D_REG_IGMP_PORT7_CONTROL    0x1c0c
#define    RTL8367D_IGMP_PORT7_CONTROL_MLDv2_OP_OFFSET    8
#define    RTL8367D_IGMP_PORT7_CONTROL_MLDv2_OP_MASK    0x300
#define    RTL8367D_IGMP_PORT7_CONTROL_MLDv1_OP_OFFSET    6
#define    RTL8367D_IGMP_PORT7_CONTROL_MLDv1_OP_MASK    0xC0
#define    RTL8367D_IGMP_PORT7_CONTROL_IGMPV3_OP_OFFSET    4
#define    RTL8367D_IGMP_PORT7_CONTROL_IGMPV3_OP_MASK    0x30
#define    RTL8367D_IGMP_PORT7_CONTROL_IGMPV2_OP_OFFSET    2
#define    RTL8367D_IGMP_PORT7_CONTROL_IGMPV2_OP_MASK    0xC
#define    RTL8367D_IGMP_PORT7_CONTROL_IGMPV1_OP_OFFSET    0
#define    RTL8367D_IGMP_PORT7_CONTROL_IGMPV1_OP_MASK    0x3

#define    RTL8367D_REG_IGMP_MLD_CFG3    0x1c15
#define    RTL8367D_IGMP_MLD_IP6_BYPASS_OFFSET    5
#define    RTL8367D_IGMP_MLD_IP6_BYPASS_MASK    0x20
#define    RTL8367D_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET    4
#define    RTL8367D_IGMP_MLD_IP4_BYPASS_239_255_255_MASK    0x10
#define    RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET    3
#define    RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_1_MASK    0x8
#define    RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET    2
#define    RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_0_MASK    0x4

/* (16'h1d00)chip_67d_reg */

#define    RTL8367D_REG_PCSXF_CFG    0x1d00
#define    RTL8367D_CFG_PCSXF_OFFSET    8
#define    RTL8367D_CFG_PCSXF_MASK    0xF00
#define    RTL8367D_CFG_RST_RXFIFO_OFFSET    3
#define    RTL8367D_CFG_RST_RXFIFO_MASK    0xF8
#define    RTL8367D_CFG_COL2RXDV_OFFSET    2
#define    RTL8367D_CFG_COL2RXDV_MASK    0x4
#define    RTL8367D_CFG_PHY_SDET_OFFSET    0
#define    RTL8367D_CFG_PHY_SDET_MASK    0x3

#define    RTL8367D_REG_PHYID_CFG0    0x1d01
#define    RTL8367D_CFG_PHYAD_14C_OFFSET    10
#define    RTL8367D_CFG_PHYAD_14C_MASK    0x400
#define    RTL8367D_CFG_PHY_BRD_MODE_OFFSET    5
#define    RTL8367D_CFG_PHY_BRD_MODE_MASK    0x3E0
#define    RTL8367D_CFG_BRD_PHYAD_OFFSET    0
#define    RTL8367D_CFG_BRD_PHYAD_MASK    0x1F

#define    RTL8367D_REG_PHYID_CFG1    0x1d02
#define    RTL8367D_CFG_MSK_MDI_OFFSET    5
#define    RTL8367D_CFG_MSK_MDI_MASK    0x3E0
#define    RTL8367D_CFG_BASE_PHYAD_OFFSET    0
#define    RTL8367D_CFG_BASE_PHYAD_MASK    0x1F

#define    RTL8367D_REG_PHY_POLL_CFG0    0x1d03
#define    RTL8367D_CFG_HOTCMD_PRD_EN_OFFSET    15
#define    RTL8367D_CFG_HOTCMD_PRD_EN_MASK    0x8000
#define    RTL8367D_CFG_HOTCMD_EN_OFFSET    12
#define    RTL8367D_CFG_HOTCMD_EN_MASK    0x7000
#define    RTL8367D_CFG_POLL_PERIOD_OFFSET    8
#define    RTL8367D_CFG_POLL_PERIOD_MASK    0xF00
#define    RTL8367D_CFG_PERI_CMDS_RD_OFFSET    4
#define    RTL8367D_CFG_PERI_CMDS_RD_MASK    0xF0
#define    RTL8367D_CFG_PERI_CMDS_WR_OFFSET    0
#define    RTL8367D_CFG_PERI_CMDS_WR_MASK    0xF

#define    RTL8367D_REG_PHY_POLL_CFG1    0x1d04

#define    RTL8367D_REG_PHY_POLL_CFG2    0x1d05

#define    RTL8367D_REG_PHY_POLL_CFG3    0x1d06

#define    RTL8367D_REG_PHY_POLL_CFG4    0x1d07

#define    RTL8367D_REG_PHY_POLL_CFG5    0x1d08

#define    RTL8367D_REG_PHY_POLL_CFG6    0x1d09

#define    RTL8367D_REG_PHY_POLL_CFG7    0x1d0a

#define    RTL8367D_REG_PHY_POLL_CFG8    0x1d0b

#define    RTL8367D_REG_PHY_POLL_CFG9    0x1d0c

#define    RTL8367D_REG_PHY_POLL_CFG10    0x1d0d

#define    RTL8367D_REG_PHY_POLL_CFG11    0x1d0e

#define    RTL8367D_REG_PHY_POLL_CFG12    0x1d0f

#define    RTL8367D_REG_EFUSE_MISC    0x1d10
#define    RTL8367D_CFG_SA_SEL_OFFSET    5
#define    RTL8367D_CFG_SA_SEL_MASK    0x20
#define    RTL8367D_CFG_PHYAD00_OFFSET    0
#define    RTL8367D_CFG_PHYAD00_MASK    0x1F

#define    RTL8367D_REG_SDS_MISC    0x1d11
#define    RTL8367D_PA33PC_EN_S0_OFFSET    11
#define    RTL8367D_PA33PC_EN_S0_MASK    0x800
#define    RTL8367D_PA12PC_EN_S0_OFFSET    10
#define    RTL8367D_PA12PC_EN_S0_MASK    0x400
#define    RTL8367D_MAC6_SEL_SDS0_OFFSET    9
#define    RTL8367D_MAC6_SEL_SDS0_MASK    0x200
#define    RTL8367D_SDS_MISC_SDS_PWR_ISO_EN_1_OFFSET    8
#define    RTL8367D_SDS_MISC_SDS_PWR_ISO_EN_1_MASK    0x100
#define    RTL8367D_SDS_MISC_SDS_FRC_REG4_EN_1_OFFSET    7
#define    RTL8367D_SDS_MISC_SDS_FRC_REG4_EN_1_MASK    0x80
#define    RTL8367D_SDS_MISC_SDS_FRC_REG4_FIB100_1_OFFSET    6
#define    RTL8367D_SDS_MISC_SDS_FRC_REG4_FIB100_1_MASK    0x40
#define    RTL8367D_SDS_MISC_CFG_UNIDIR_TX_OFFSET    5
#define    RTL8367D_SDS_MISC_CFG_UNIDIR_TX_MASK    0x20
#define    RTL8367D_CFG_SDS_MODE_OFFSET    0
#define    RTL8367D_CFG_SDS_MODE_MASK    0x1F

#define    RTL8367D_REG_BCAM_SETTING    0x1d13
#define    RTL8367D_CFG_BCAM_MDS_OFFSET    3
#define    RTL8367D_CFG_BCAM_MDS_MASK    0x18
#define    RTL8367D_CFG_BCAM_RDS_OFFSET    0
#define    RTL8367D_CFG_BCAM_RDS_MASK    0x7

#define    RTL8367D_REG_GPHY_ACS_MISC    0x1d14
#define    RTL8367D_CFG_SEL_GPHY_SMI_OFFSET    3
#define    RTL8367D_CFG_SEL_GPHY_SMI_MASK    0x8
#define    RTL8367D_CFG_BRD_PHYIDX_OFFSET    0
#define    RTL8367D_CFG_BRD_PHYIDX_MASK    0x7

#define    RTL8367D_REG_GPHY_OCP_MSB_0    0x1d15
#define    RTL8367D_CFG_CPU_OCPADR_MSB_OFFSET    6
#define    RTL8367D_CFG_CPU_OCPADR_MSB_MASK    0xFC0
#define    RTL8367D_CFG_DW8051_OCPADR_MSB_OFFSET    0
#define    RTL8367D_CFG_DW8051_OCPADR_MSB_MASK    0x3F

#define    RTL8367D_REG_GPHY_OCP_MSB_1    0x1d16
#define    RTL8367D_CFG_PATCH_OCPADR_MSB_OFFSET    6
#define    RTL8367D_CFG_PATCH_OCPADR_MSB_MASK    0xFC0
#define    RTL8367D_CFG_PHYSTS_OCPADR_MSB_OFFSET    0
#define    RTL8367D_CFG_PHYSTS_OCPADR_MSB_MASK    0x3F

#define    RTL8367D_REG_GPHY_OCP_MSB_2    0x1d17
#define    RTL8367D_CFG_RRCP_OCPADR_MSB_OFFSET    6
#define    RTL8367D_CFG_RRCP_OCPADR_MSB_MASK    0xFC0
#define    RTL8367D_CFG_RTCT_OCPADR_MSB_OFFSET    0
#define    RTL8367D_CFG_RTCT_OCPADR_MSB_MASK    0x3F

#define    RTL8367D_REG_GPHY_OCP_MSB_3    0x1d18
#define    RTL8367D_GPHY_OCP_MSB_3_OFFSET    0
#define    RTL8367D_GPHY_OCP_MSB_3_MASK    0x3F

#define    RTL8367D_REG_GPIO_67C_I_X0    0x1d19

#define    RTL8367D_REG_GPIO_67C_I_X1    0x1d1a

#define    RTL8367D_REG_GPIO_67C_I_X2    0x1d1b

#define    RTL8367D_REG_GPIO_67C_I_X3    0x1d1c
#define    RTL8367D_GPIO_67C_I_X3_OFFSET    0
#define    RTL8367D_GPIO_67C_I_X3_MASK    0x3FFF

#define    RTL8367D_REG_GPIO_67C_O_X0    0x1d1d

#define    RTL8367D_REG_GPIO_67C_O_X1    0x1d1e

#define    RTL8367D_REG_GPIO_67C_O_X2    0x1d1f

#define    RTL8367D_REG_GPIO_67C_O_X3    0x1d20
#define    RTL8367D_GPIO_67C_O_X3_OFFSET    0
#define    RTL8367D_GPIO_67C_O_X3_MASK    0x3FFF

#define    RTL8367D_REG_GPIO_67C_OE_X0    0x1d21

#define    RTL8367D_REG_GPIO_67C_OE_X1    0x1d22

#define    RTL8367D_REG_GPIO_67C_OE_X2    0x1d23

#define    RTL8367D_REG_GPIO_67C_OE_X3    0x1d24
#define    RTL8367D_GPIO_67C_OE_X3_OFFSET    0
#define    RTL8367D_GPIO_67C_OE_X3_MASK    0x3FFF

#define    RTL8367D_REG_GPIO_MODE_67C_X0    0x1d25

#define    RTL8367D_REG_GPIO_MODE_67C_X1    0x1d26

#define    RTL8367D_REG_GPIO_MODE_67C_X2    0x1d27

#define    RTL8367D_REG_GPIO_MODE_67C_X3    0x1d28
#define    RTL8367D_GPIO_MODE_67C_X3_OFFSET    0
#define    RTL8367D_GPIO_MODE_67C_X3_MASK    0x3FFF

#define    RTL8367D_REG_WGPHY_MISC_0    0x1d29
#define    RTL8367D_CFG_INIPHY_PWRUP_OFFSET    5
#define    RTL8367D_CFG_INIPHY_PWRUP_MASK    0x3E0
#define    RTL8367D_CFG_INIPHY_DISGIGA_OFFSET    0
#define    RTL8367D_CFG_INIPHY_DISGIGA_MASK    0x1F

#define    RTL8367D_REG_WGPHY_MISC_1    0x1d2a
#define    RTL8367D_WGPHY_MISC_1_OFFSET    0
#define    RTL8367D_WGPHY_MISC_1_MASK    0xFF

#define    RTL8367D_REG_WGPHY_MISC_2    0x1d2b
#define    RTL8367D_WGPHY_MISC_2_OFFSET    0
#define    RTL8367D_WGPHY_MISC_2_MASK    0x3FF

#define    RTL8367D_REG_CFG_AFBK_GPHY_0    0x1d2c
#define    RTL8367D_CFG_AFBK_GPHY_0_OFFSET    0
#define    RTL8367D_CFG_AFBK_GPHY_0_MASK    0x1F

#define    RTL8367D_REG_CFG_AFBK_GPHY_1    0x1d2d
#define    RTL8367D_CFG_AFBK_GPHY_1_OFFSET    0
#define    RTL8367D_CFG_AFBK_GPHY_1_MASK    0xFFF

#define    RTL8367D_REG_EF_SLV_CTRL_0    0x1d2e
#define    RTL8367D_EF_SLV_BUSY_OFFSET    11
#define    RTL8367D_EF_SLV_BUSY_MASK    0x800
#define    RTL8367D_EF_SLV_ACK_OFFSET    10
#define    RTL8367D_EF_SLV_ACK_MASK    0x400
#define    RTL8367D_EF_SLV_A_OFFSET    2
#define    RTL8367D_EF_SLV_A_MASK    0x3FC
#define    RTL8367D_EF_SLV_WE_OFFSET    1
#define    RTL8367D_EF_SLV_WE_MASK    0x2
#define    RTL8367D_EF_SLV_CE_OFFSET    0
#define    RTL8367D_EF_SLV_CE_MASK    0x1

#define    RTL8367D_REG_EF_SLV_CTRL_1    0x1d2f

#define    RTL8367D_REG_EF_SLV_CTRL_2    0x1d30

#define    RTL8367D_REG_EFUSE_MISC_1    0x1d31

#define    RTL8367D_REG_IO_MISC_FUNC    0x1d32
#define    RTL8367D_TST_MODE_OFFSET    3
#define    RTL8367D_TST_MODE_MASK    0x8
#define    RTL8367D_UART_EN_OFFSET    2
#define    RTL8367D_UART_EN_MASK    0x4
#define    RTL8367D_INT_EN_OFFSET    1
#define    RTL8367D_INT_EN_MASK    0x2
#define    RTL8367D_BUZ_EN_OFFSET    0
#define    RTL8367D_BUZ_EN_MASK    0x1

#define    RTL8367D_REG_HTRAM_DVS    0x1d33
#define    RTL8367D_HTRAM_DVS_OFFSET    0
#define    RTL8367D_HTRAM_DVS_MASK    0x1

#define    RTL8367D_REG_EF_SLV_CTRL_3    0x1d34
#define    RTL8367D_EF_SLV_CTRL_3_OFFSET    0
#define    RTL8367D_EF_SLV_CTRL_3_MASK    0x1

#define    RTL8367D_REG_INBAND_EN14C    0x1d35
#define    RTL8367D_INBAND_EN14C_OFFSET    0
#define    RTL8367D_INBAND_EN14C_MASK    0x1

#define    RTL8367D_REG_CFG_SWR_L    0x1d36
#define    RTL8367D_ANARG_RDY_SWR_L_OFFSET    14
#define    RTL8367D_ANARG_RDY_SWR_L_MASK    0x4000
#define    RTL8367D_ANARG_VALID_SWR_L_OFFSET    13
#define    RTL8367D_ANARG_VALID_SWR_L_MASK    0x2000
#define    RTL8367D_SAW_SWR_L_OFFSET    9
#define    RTL8367D_SAW_SWR_L_MASK    0x1E00
#define    RTL8367D_SAW_VALID_SWR_L_OFFSET    8
#define    RTL8367D_SAW_VALID_SWR_L_MASK    0x100
#define    RTL8367D_UPS_DBGO_L_OFFSET    0
#define    RTL8367D_UPS_DBGO_L_MASK    0xFF

#define    RTL8367D_REG_BTCAM_CTRL    0x1d37
#define    RTL8367D_BTCAM_CTRL_TCAM_RDS_OFFSET    2
#define    RTL8367D_BTCAM_CTRL_TCAM_RDS_MASK    0x1C
#define    RTL8367D_BTCAM_CTRL_TCAM_MDS_OFFSET    0
#define    RTL8367D_BTCAM_CTRL_TCAM_MDS_MASK    0x3

#define    RTL8367D_REG_PBRAM_BISR_CTRL    0x1d38
#define    RTL8367D_HAS_HLDRMP_MD_OFFSET    9
#define    RTL8367D_HAS_HLDRMP_MD_MASK    0x200
#define    RTL8367D_PB_HLDRMP_MD_OFFSET    8
#define    RTL8367D_PB_HLDRMP_MD_MASK    0x100
#define    RTL8367D_HAS_BISR_BIRSTN_OFFSET    7
#define    RTL8367D_HAS_BISR_BIRSTN_MASK    0x80
#define    RTL8367D_SEC_RUN_HSA_OFFSET    6
#define    RTL8367D_SEC_RUN_HSA_MASK    0x40
#define    RTL8367D_HAS_HLDRMP_VAL_OFFSET    5
#define    RTL8367D_HAS_HLDRMP_VAL_MASK    0x20
#define    RTL8367D_HAS_BISR_PWRSTN_OFFSET    4
#define    RTL8367D_HAS_BISR_PWRSTN_MASK    0x10
#define    RTL8367D_SEC_RUN_PB_OFFSET    3
#define    RTL8367D_SEC_RUN_PB_MASK    0x8
#define    RTL8367D_PB_HLDRMP_VAL_OFFSET    2
#define    RTL8367D_PB_HLDRMP_VAL_MASK    0x4
#define    RTL8367D_PB_BISR_BIRSTN_OFFSET    1
#define    RTL8367D_PB_BISR_BIRSTN_MASK    0x2
#define    RTL8367D_PB_BISR_PWRSTN_OFFSET    0
#define    RTL8367D_PB_BISR_PWRSTN_MASK    0x1

#define    RTL8367D_REG_CVLANRAM_BISR_CTRL    0x1d39
#define    RTL8367D_SEC_RUN_CVLAN_OFFSET    4
#define    RTL8367D_SEC_RUN_CVLAN_MASK    0x10
#define    RTL8367D_CVALN_HLDRMP_MD_OFFSET    3
#define    RTL8367D_CVALN_HLDRMP_MD_MASK    0x8
#define    RTL8367D_CVALN_HLDRMP_VAL_OFFSET    2
#define    RTL8367D_CVALN_HLDRMP_VAL_MASK    0x4
#define    RTL8367D_CVLAN_BISR_BIRSTN_OFFSET    1
#define    RTL8367D_CVLAN_BISR_BIRSTN_MASK    0x2
#define    RTL8367D_CVLAN_BISR_PWRSTN_OFFSET    0
#define    RTL8367D_CVLAN_BISR_PWRSTN_MASK    0x1

#define    RTL8367D_REG_CFG_1588_TIMER_EN_GPI    0x1d3a
#define    RTL8367D_CFG_1588_TIMER_EN_GPI_OFFSET    0
#define    RTL8367D_CFG_1588_TIMER_EN_GPI_MASK    0x1

#define    RTL8367D_REG_MDIO_PRMB_SUPP    0x1d3b
#define    RTL8367D_SMT_EXT1CK_EN_OFFSET    15
#define    RTL8367D_SMT_EXT1CK_EN_MASK    0x8000
#define    RTL8367D_FIB_HIPRI_OFFSET    14
#define    RTL8367D_FIB_HIPRI_MASK    0x4000
#define    RTL8367D_SMT_EN_OFFSET    13
#define    RTL8367D_SMT_EN_MASK    0x2000
#define    RTL8367D_P4_FB_CPL_OFFSET    12
#define    RTL8367D_P4_FB_CPL_MASK    0x1000
#define    RTL8367D_P3_FB_CPL_OFFSET    11
#define    RTL8367D_P3_FB_CPL_MASK    0x800
#define    RTL8367D_P2_FB_CPL_OFFSET    10
#define    RTL8367D_P2_FB_CPL_MASK    0x400
#define    RTL8367D_P1_FB_CPL_OFFSET    9
#define    RTL8367D_P1_FB_CPL_MASK    0x200
#define    RTL8367D_P0_FB_CPL_OFFSET    8
#define    RTL8367D_P0_FB_CPL_MASK    0x100
#define    RTL8367D_DBG_PKG_8367N_OFFSET    7
#define    RTL8367D_DBG_PKG_8367N_MASK    0x80
#define    RTL8367D_DBG_PKG_8367VB_OFFSET    6
#define    RTL8367D_DBG_PKG_8367VB_MASK    0x40
#define    RTL8367D_CFG_DEBUG_EN_OFFSET    5
#define    RTL8367D_CFG_DEBUG_EN_MASK    0x20
#define    RTL8367D_CFG_TMR_ACK_OFFSET    1
#define    RTL8367D_CFG_TMR_ACK_MASK    0x1E
#define    RTL8367D_CFG_PRMB_SUPP_OFFSET    0
#define    RTL8367D_CFG_PRMB_SUPP_MASK    0x1

#define    RTL8367D_REG_BOND4READ    0x1d3c
#define    RTL8367D_SPDUP_OFFSET    13
#define    RTL8367D_SPDUP_MASK    0x2000
#define    RTL8367D_DBGO_SEL_EN_PAD_OFFSET    12
#define    RTL8367D_DBGO_SEL_EN_PAD_MASK    0x1000
#define    RTL8367D_BOND_DEGLITCH_ENB_OFFSET    11
#define    RTL8367D_BOND_DEGLITCH_ENB_MASK    0x800
#define    RTL8367D_BOND_RSV1_OFFSET    10
#define    RTL8367D_BOND_RSV1_MASK    0x400
#define    RTL8367D_BOND_SYSCLK_OFFSET    7
#define    RTL8367D_BOND_SYSCLK_MASK    0x180
#define    RTL8367D_BOND_DIS_TABLE_INIT_OFFSET    4
#define    RTL8367D_BOND_DIS_TABLE_INIT_MASK    0x10
#define    RTL8367D_BOND_BYP_AFE_PLL_OFFSET    3
#define    RTL8367D_BOND_BYP_AFE_PLL_MASK    0x8
#define    RTL8367D_BOND_BYP_AFE_POR_OFFSET    2
#define    RTL8367D_BOND_BYP_AFE_POR_MASK    0x4
#define    RTL8367D_BOND_EF_EN_OFFSET    0
#define    RTL8367D_BOND_EF_EN_MASK    0x1

#define    RTL8367D_REG_REG_TO_ECO0    0x1d3d

#define    RTL8367D_REG_REG_TO_ECO1    0x1d3e

#define    RTL8367D_REG_REG_TO_ECO2    0x1d3f

#define    RTL8367D_REG_REG_TO_ECO4    0x1d41
#define    RTL8367D_CFG_SLED_CLKDUTY_OFFSET    15
#define    RTL8367D_CFG_SLED_CLKDUTY_MASK    0x8000
#define    RTL8367D_CFG_ECO_SEL_SPD_OFFSET    12
#define    RTL8367D_CFG_ECO_SEL_SPD_MASK    0x1000
#define    RTL8367D_CFG_DIS_LNKDN_FRC_OFFSET    9
#define    RTL8367D_CFG_DIS_LNKDN_FRC_MASK    0x200
#define    RTL8367D_MAC6_FIB2_OFFSET    7
#define    RTL8367D_MAC6_FIB2_MASK    0x80
#define    RTL8367D_MAC6_FIB_OFFSET    5
#define    RTL8367D_MAC6_FIB_MASK    0x20
#define    RTL8367D_STRAP_EEE_EN_OFFSET    0
#define    RTL8367D_STRAP_EEE_EN_MASK    0x1F

#define    RTL8367D_REG_PHYSTS_CTRL0    0x1d42
#define    RTL8367D_SPD_2P5G_LNKUP_DLY_OFFSET    13
#define    RTL8367D_SPD_2P5G_LNKUP_DLY_MASK    0x6000
#define    RTL8367D_SPD_ABLITY_EN_MAC_OFFSET    7
#define    RTL8367D_SPD_ABLITY_EN_MAC_MASK    0x1F80
#define    RTL8367D_BYPASS_SPD_ABLITY_EN_MAC_OFFSET    6
#define    RTL8367D_BYPASS_SPD_ABLITY_EN_MAC_MASK    0x40
#define    RTL8367D_LNKUP_DLY_EN_OFFSET    4
#define    RTL8367D_LNKUP_DLY_EN_MASK    0x10
#define    RTL8367D_GE_100M_LNKUP_DLY_OFFSET    2
#define    RTL8367D_GE_100M_LNKUP_DLY_MASK    0xC
#define    RTL8367D_PHYSTS_10M_LNKUP_DLY_OFFSET    0
#define    RTL8367D_PHYSTS_10M_LNKUP_DLY_MASK    0x3

#define    RTL8367D_REG_PHYSTS_CTRL1    0x1d43
#define    RTL8367D_PHYSTS_CTRL1_OFFSET    0
#define    RTL8367D_PHYSTS_CTRL1_MASK    0xFF

#define    RTL8367D_REG_SSC_CTRL0_0    0x1d44
#define    RTL8367D_SSC_CTRL0_0_SSC_TYPE_OFFSET    13
#define    RTL8367D_SSC_CTRL0_0_SSC_TYPE_MASK    0x2000
#define    RTL8367D_SSC_CTRL0_0_PHASE_LIM_SEL_OFFSET    5
#define    RTL8367D_SSC_CTRL0_0_PHASE_LIM_SEL_MASK    0x1FE0
#define    RTL8367D_SSC_CTRL0_0_PHASE_LIM_EN_OFFSET    4
#define    RTL8367D_SSC_CTRL0_0_PHASE_LIM_EN_MASK    0x10
#define    RTL8367D_SSC_CTRL0_0_DLL_MODE_OFFSET    2
#define    RTL8367D_SSC_CTRL0_0_DLL_MODE_MASK    0xC
#define    RTL8367D_SSC_CTRL0_0_SSC_EN_OFFSET    1
#define    RTL8367D_SSC_CTRL0_0_SSC_EN_MASK    0x2
#define    RTL8367D_SSC_CTRL0_0_SSC_MODE_OFFSET    0
#define    RTL8367D_SSC_CTRL0_0_SSC_MODE_MASK    0x1

#define    RTL8367D_REG_SSC_RDM_SEED    0x1d45

#define    RTL8367D_REG_SSC_PN_POLY_SEL    0x1d46

#define    RTL8367D_REG_SSC_CTRL0_3    0x1d47
#define    RTL8367D_SSC_CTRL0_3_PHSFT_CNT_OFFSET    8
#define    RTL8367D_SSC_CTRL0_3_PHSFT_CNT_MASK    0x7F00
#define    RTL8367D_SSC_CTRL0_3_PHSFT_A_OFFSET    7
#define    RTL8367D_SSC_CTRL0_3_PHSFT_A_MASK    0x80
#define    RTL8367D_SSC_CTRL0_3_PHSFT_B_OFFSET    6
#define    RTL8367D_SSC_CTRL0_3_PHSFT_B_MASK    0x40
#define    RTL8367D_SSC_CTRL0_3_PHSFT_UPDN_OFFSET    5
#define    RTL8367D_SSC_CTRL0_3_PHSFT_UPDN_MASK    0x20
#define    RTL8367D_SSC_CTRL0_3_PHSFT_PRD_OFFSET    4
#define    RTL8367D_SSC_CTRL0_3_PHSFT_PRD_MASK    0x10
#define    RTL8367D_SSC_CTRL0_3_PN_POLY_DEG_OFFSET    0
#define    RTL8367D_SSC_CTRL0_3_PN_POLY_DEG_MASK    0xF

#define    RTL8367D_REG_SSC_CTRL0_4    0x1d48
#define    RTL8367D_SSC_CTRL0_4_SSC_UP1DN0_OFFSET    15
#define    RTL8367D_SSC_CTRL0_4_SSC_UP1DN0_MASK    0x8000
#define    RTL8367D_SSC_CTRL0_4_SSC_PERIOD_OFFSET    8
#define    RTL8367D_SSC_CTRL0_4_SSC_PERIOD_MASK    0x7F00
#define    RTL8367D_SSC_CTRL0_4_SSC_OFFSET_OFFSET    0
#define    RTL8367D_SSC_CTRL0_4_SSC_OFFSET_MASK    0xFF

#define    RTL8367D_REG_SSC_CTRL0_5    0x1d49
#define    RTL8367D_SSC_CTRL0_5_PH_OFS_TOG_OFFSET    15
#define    RTL8367D_SSC_CTRL0_5_PH_OFS_TOG_MASK    0x8000
#define    RTL8367D_SSC_CTRL0_5_PH_OFS_OFFSET    10
#define    RTL8367D_SSC_CTRL0_5_PH_OFS_MASK    0x7C00
#define    RTL8367D_SSC_CTRL0_5_SSC_STEP_OFFSET    4
#define    RTL8367D_SSC_CTRL0_5_SSC_STEP_MASK    0x3F0
#define    RTL8367D_SSC_CTRL0_5_SSC_TEST_MODE_OFFSET    2
#define    RTL8367D_SSC_CTRL0_5_SSC_TEST_MODE_MASK    0xC
#define    RTL8367D_SSC_CTRL0_5_SSC_PH_CFG_OFFSET    0
#define    RTL8367D_SSC_CTRL0_5_SSC_PH_CFG_MASK    0x3

#define    RTL8367D_REG_SSC_STS0    0x1d4a
#define    RTL8367D_SSC_STS0_OFS_BUSY_OFFSET    13
#define    RTL8367D_SSC_STS0_OFS_BUSY_MASK    0x2000
#define    RTL8367D_SSC_STS0_OFS_TOTAL_R_OFFSET    8
#define    RTL8367D_SSC_STS0_OFS_TOTAL_R_MASK    0x1F00
#define    RTL8367D_SSC_STS0_CNT_GRY0_OFFSET    4
#define    RTL8367D_SSC_STS0_CNT_GRY0_MASK    0xF0
#define    RTL8367D_SSC_STS0_OFS_GRY0_OFFSET    0
#define    RTL8367D_SSC_STS0_OFS_GRY0_MASK    0xF

#define    RTL8367D_REG_SSC_CTRL1_0    0x1d4b
#define    RTL8367D_SSC_CTRL1_0_SSC_TYPE_OFFSET    13
#define    RTL8367D_SSC_CTRL1_0_SSC_TYPE_MASK    0x2000
#define    RTL8367D_SSC_CTRL1_0_PHASE_LIM_SEL_OFFSET    5
#define    RTL8367D_SSC_CTRL1_0_PHASE_LIM_SEL_MASK    0x1FE0
#define    RTL8367D_SSC_CTRL1_0_PHASE_LIM_EN_OFFSET    4
#define    RTL8367D_SSC_CTRL1_0_PHASE_LIM_EN_MASK    0x10
#define    RTL8367D_SSC_CTRL1_0_DLL_MODE_OFFSET    2
#define    RTL8367D_SSC_CTRL1_0_DLL_MODE_MASK    0xC
#define    RTL8367D_SSC_CTRL1_0_SSC_EN_OFFSET    1
#define    RTL8367D_SSC_CTRL1_0_SSC_EN_MASK    0x2
#define    RTL8367D_SSC_CTRL1_0_SSC_MODE_OFFSET    0
#define    RTL8367D_SSC_CTRL1_0_SSC_MODE_MASK    0x1

#define    RTL8367D_REG_SSC_RDM_SEED1    0x1d4c

#define    RTL8367D_REG_SSC_PN_POLY_SEL1    0x1d4d

#define    RTL8367D_REG_SSC_CTRL1_3    0x1d4e
#define    RTL8367D_SSC_CTRL1_3_PHSFT_CNT_OFFSET    8
#define    RTL8367D_SSC_CTRL1_3_PHSFT_CNT_MASK    0x7F00
#define    RTL8367D_SSC_CTRL1_3_PHSFT_A_OFFSET    7
#define    RTL8367D_SSC_CTRL1_3_PHSFT_A_MASK    0x80
#define    RTL8367D_SSC_CTRL1_3_PHSFT_B_OFFSET    6
#define    RTL8367D_SSC_CTRL1_3_PHSFT_B_MASK    0x40
#define    RTL8367D_SSC_CTRL1_3_PHSFT_UPDN_OFFSET    5
#define    RTL8367D_SSC_CTRL1_3_PHSFT_UPDN_MASK    0x20
#define    RTL8367D_SSC_CTRL1_3_PHSFT_PRD_OFFSET    4
#define    RTL8367D_SSC_CTRL1_3_PHSFT_PRD_MASK    0x10
#define    RTL8367D_SSC_CTRL1_3_PN_POLY_DEG_OFFSET    0
#define    RTL8367D_SSC_CTRL1_3_PN_POLY_DEG_MASK    0xF

#define    RTL8367D_REG_SSC_CTRL1_4    0x1d4f
#define    RTL8367D_SSC_CTRL1_4_SSC_UP1DN0_OFFSET    15
#define    RTL8367D_SSC_CTRL1_4_SSC_UP1DN0_MASK    0x8000
#define    RTL8367D_SSC_CTRL1_4_SSC_PERIOD_OFFSET    8
#define    RTL8367D_SSC_CTRL1_4_SSC_PERIOD_MASK    0x7F00
#define    RTL8367D_SSC_CTRL1_4_SSC_OFFSET_OFFSET    0
#define    RTL8367D_SSC_CTRL1_4_SSC_OFFSET_MASK    0xFF

#define    RTL8367D_REG_SSC_CTRL1_5    0x1d50
#define    RTL8367D_SSC_CTRL1_5_PH_OFS_TOG_OFFSET    15
#define    RTL8367D_SSC_CTRL1_5_PH_OFS_TOG_MASK    0x8000
#define    RTL8367D_SSC_CTRL1_5_PH_OFS_OFFSET    10
#define    RTL8367D_SSC_CTRL1_5_PH_OFS_MASK    0x7C00
#define    RTL8367D_SSC_CTRL1_5_SSC_STEP_OFFSET    4
#define    RTL8367D_SSC_CTRL1_5_SSC_STEP_MASK    0x3F0
#define    RTL8367D_SSC_CTRL1_5_SSC_TEST_MODE_OFFSET    2
#define    RTL8367D_SSC_CTRL1_5_SSC_TEST_MODE_MASK    0xC
#define    RTL8367D_SSC_CTRL1_5_SSC_PH_CFG_OFFSET    0
#define    RTL8367D_SSC_CTRL1_5_SSC_PH_CFG_MASK    0x3

#define    RTL8367D_REG_SSC_STS1    0x1d51
#define    RTL8367D_SSC_STS1_OFS_BUSY_OFFSET    13
#define    RTL8367D_SSC_STS1_OFS_BUSY_MASK    0x2000
#define    RTL8367D_SSC_STS1_OFS_TOTAL_R_OFFSET    8
#define    RTL8367D_SSC_STS1_OFS_TOTAL_R_MASK    0x1F00
#define    RTL8367D_SSC_STS1_CNT_GRY0_OFFSET    4
#define    RTL8367D_SSC_STS1_CNT_GRY0_MASK    0xF0
#define    RTL8367D_SSC_STS1_OFS_GRY0_OFFSET    0
#define    RTL8367D_SSC_STS1_OFS_GRY0_MASK    0xF

#define    RTL8367D_REG_SSC_CTRL2_0    0x1d52
#define    RTL8367D_SSC_CTRL2_0_SSC_TYPE_OFFSET    13
#define    RTL8367D_SSC_CTRL2_0_SSC_TYPE_MASK    0x2000
#define    RTL8367D_SSC_CTRL2_0_PHASE_LIM_SEL_OFFSET    5
#define    RTL8367D_SSC_CTRL2_0_PHASE_LIM_SEL_MASK    0x1FE0
#define    RTL8367D_SSC_CTRL2_0_PHASE_LIM_EN_OFFSET    4
#define    RTL8367D_SSC_CTRL2_0_PHASE_LIM_EN_MASK    0x10
#define    RTL8367D_SSC_CTRL2_0_DLL_MODE_OFFSET    2
#define    RTL8367D_SSC_CTRL2_0_DLL_MODE_MASK    0xC
#define    RTL8367D_SSC_CTRL2_0_SSC_EN_OFFSET    1
#define    RTL8367D_SSC_CTRL2_0_SSC_EN_MASK    0x2
#define    RTL8367D_SSC_CTRL2_0_SSC_MODE_OFFSET    0
#define    RTL8367D_SSC_CTRL2_0_SSC_MODE_MASK    0x1

#define    RTL8367D_REG_SSC_RDM_SEED2    0x1d53

#define    RTL8367D_REG_SSC_PN_POLY_SEL2    0x1d54

#define    RTL8367D_REG_SSC_CTRL2_3    0x1d55
#define    RTL8367D_SSC_CTRL2_3_PHSFT_CNT_OFFSET    8
#define    RTL8367D_SSC_CTRL2_3_PHSFT_CNT_MASK    0x7F00
#define    RTL8367D_SSC_CTRL2_3_PHSFT_A_OFFSET    7
#define    RTL8367D_SSC_CTRL2_3_PHSFT_A_MASK    0x80
#define    RTL8367D_SSC_CTRL2_3_PHSFT_B_OFFSET    6
#define    RTL8367D_SSC_CTRL2_3_PHSFT_B_MASK    0x40
#define    RTL8367D_SSC_CTRL2_3_PHSFT_UPDN_OFFSET    5
#define    RTL8367D_SSC_CTRL2_3_PHSFT_UPDN_MASK    0x20
#define    RTL8367D_SSC_CTRL2_3_PHSFT_PRD_OFFSET    4
#define    RTL8367D_SSC_CTRL2_3_PHSFT_PRD_MASK    0x10
#define    RTL8367D_SSC_CTRL2_3_PN_POLY_DEG_OFFSET    0
#define    RTL8367D_SSC_CTRL2_3_PN_POLY_DEG_MASK    0xF

#define    RTL8367D_REG_SSC_CTRL2_4    0x1d56
#define    RTL8367D_SSC_CTRL2_4_SSC_UP1DN0_OFFSET    15
#define    RTL8367D_SSC_CTRL2_4_SSC_UP1DN0_MASK    0x8000
#define    RTL8367D_SSC_CTRL2_4_SSC_PERIOD_OFFSET    8
#define    RTL8367D_SSC_CTRL2_4_SSC_PERIOD_MASK    0x7F00
#define    RTL8367D_SSC_CTRL2_4_SSC_OFFSET_OFFSET    0
#define    RTL8367D_SSC_CTRL2_4_SSC_OFFSET_MASK    0xFF

#define    RTL8367D_REG_SSC_CTRL2_5    0x1d57
#define    RTL8367D_SSC_CTRL2_5_PH_OFS_TOG_OFFSET    15
#define    RTL8367D_SSC_CTRL2_5_PH_OFS_TOG_MASK    0x8000
#define    RTL8367D_SSC_CTRL2_5_PH_OFS_OFFSET    10
#define    RTL8367D_SSC_CTRL2_5_PH_OFS_MASK    0x7C00
#define    RTL8367D_SSC_CTRL2_5_SSC_STEP_OFFSET    4
#define    RTL8367D_SSC_CTRL2_5_SSC_STEP_MASK    0x3F0
#define    RTL8367D_SSC_CTRL2_5_SSC_TEST_MODE_OFFSET    2
#define    RTL8367D_SSC_CTRL2_5_SSC_TEST_MODE_MASK    0xC
#define    RTL8367D_SSC_CTRL2_5_SSC_PH_CFG_OFFSET    0
#define    RTL8367D_SSC_CTRL2_5_SSC_PH_CFG_MASK    0x3

#define    RTL8367D_REG_SSC_STS2    0x1d58
#define    RTL8367D_SSC_STS2_OFS_BUSY_OFFSET    13
#define    RTL8367D_SSC_STS2_OFS_BUSY_MASK    0x2000
#define    RTL8367D_SSC_STS2_OFS_TOTAL_R_OFFSET    8
#define    RTL8367D_SSC_STS2_OFS_TOTAL_R_MASK    0x1F00
#define    RTL8367D_SSC_STS2_CNT_GRY0_OFFSET    4
#define    RTL8367D_SSC_STS2_CNT_GRY0_MASK    0xF0
#define    RTL8367D_SSC_STS2_OFS_GRY0_OFFSET    0
#define    RTL8367D_SSC_STS2_OFS_GRY0_MASK    0xF

#define    RTL8367D_REG_SSC_CTRL3_0    0x1d59
#define    RTL8367D_SSC_CTRL3_0_SSC_TYPE_OFFSET    13
#define    RTL8367D_SSC_CTRL3_0_SSC_TYPE_MASK    0x2000
#define    RTL8367D_SSC_CTRL3_0_PHASE_LIM_SEL_OFFSET    5
#define    RTL8367D_SSC_CTRL3_0_PHASE_LIM_SEL_MASK    0x1FE0
#define    RTL8367D_SSC_CTRL3_0_PHASE_LIM_EN_OFFSET    4
#define    RTL8367D_SSC_CTRL3_0_PHASE_LIM_EN_MASK    0x10
#define    RTL8367D_SSC_CTRL3_0_DLL_MODE_OFFSET    2
#define    RTL8367D_SSC_CTRL3_0_DLL_MODE_MASK    0xC
#define    RTL8367D_SSC_CTRL3_0_SSC_EN_OFFSET    1
#define    RTL8367D_SSC_CTRL3_0_SSC_EN_MASK    0x2
#define    RTL8367D_SSC_CTRL3_0_SSC_MODE_OFFSET    0
#define    RTL8367D_SSC_CTRL3_0_SSC_MODE_MASK    0x1

#define    RTL8367D_REG_SSC_RDM_SEED3    0x1d5a

#define    RTL8367D_REG_SSC_PN_POLY_SEL3    0x1d5b

#define    RTL8367D_REG_SSC_CTRL3_3    0x1d5c
#define    RTL8367D_SSC_CTRL3_3_PHSFT_CNT_OFFSET    8
#define    RTL8367D_SSC_CTRL3_3_PHSFT_CNT_MASK    0x7F00
#define    RTL8367D_SSC_CTRL3_3_PHSFT_A_OFFSET    7
#define    RTL8367D_SSC_CTRL3_3_PHSFT_A_MASK    0x80
#define    RTL8367D_SSC_CTRL3_3_PHSFT_B_OFFSET    6
#define    RTL8367D_SSC_CTRL3_3_PHSFT_B_MASK    0x40
#define    RTL8367D_SSC_CTRL3_3_PHSFT_UPDN_OFFSET    5
#define    RTL8367D_SSC_CTRL3_3_PHSFT_UPDN_MASK    0x20
#define    RTL8367D_SSC_CTRL3_3_PHSFT_PRD_OFFSET    4
#define    RTL8367D_SSC_CTRL3_3_PHSFT_PRD_MASK    0x10
#define    RTL8367D_SSC_CTRL3_3_PN_POLY_DEG_OFFSET    0
#define    RTL8367D_SSC_CTRL3_3_PN_POLY_DEG_MASK    0xF

#define    RTL8367D_REG_SSC_CTRL3_4    0x1d5d
#define    RTL8367D_SSC_CTRL3_4_SSC_UP1DN0_OFFSET    15
#define    RTL8367D_SSC_CTRL3_4_SSC_UP1DN0_MASK    0x8000
#define    RTL8367D_SSC_CTRL3_4_SSC_PERIOD_OFFSET    8
#define    RTL8367D_SSC_CTRL3_4_SSC_PERIOD_MASK    0x7F00
#define    RTL8367D_SSC_CTRL3_4_SSC_OFFSET_OFFSET    0
#define    RTL8367D_SSC_CTRL3_4_SSC_OFFSET_MASK    0xFF

#define    RTL8367D_REG_SSC_CTRL3_5    0x1d5e
#define    RTL8367D_SSC_CTRL3_5_PH_OFS_TOG_OFFSET    15
#define    RTL8367D_SSC_CTRL3_5_PH_OFS_TOG_MASK    0x8000
#define    RTL8367D_SSC_CTRL3_5_PH_OFS_OFFSET    10
#define    RTL8367D_SSC_CTRL3_5_PH_OFS_MASK    0x7C00
#define    RTL8367D_SSC_CTRL3_5_SSC_STEP_OFFSET    4
#define    RTL8367D_SSC_CTRL3_5_SSC_STEP_MASK    0x3F0
#define    RTL8367D_SSC_CTRL3_5_SSC_TEST_MODE_OFFSET    2
#define    RTL8367D_SSC_CTRL3_5_SSC_TEST_MODE_MASK    0xC
#define    RTL8367D_SSC_CTRL3_5_SSC_PH_CFG_OFFSET    0
#define    RTL8367D_SSC_CTRL3_5_SSC_PH_CFG_MASK    0x3

#define    RTL8367D_REG_SSC_STS3    0x1d5f
#define    RTL8367D_SSC_STS3_OFS_BUSY_OFFSET    13
#define    RTL8367D_SSC_STS3_OFS_BUSY_MASK    0x2000
#define    RTL8367D_SSC_STS3_OFS_TOTAL_R_OFFSET    8
#define    RTL8367D_SSC_STS3_OFS_TOTAL_R_MASK    0x1F00
#define    RTL8367D_SSC_STS3_CNT_GRY0_OFFSET    4
#define    RTL8367D_SSC_STS3_CNT_GRY0_MASK    0xF0
#define    RTL8367D_SSC_STS3_OFS_GRY0_OFFSET    0
#define    RTL8367D_SSC_STS3_OFS_GRY0_MASK    0xF

#define    RTL8367D_REG_PHY_POLL_CFG13    0x1d60

#define    RTL8367D_REG_PHY_POLL_CFG14    0x1d61

#define    RTL8367D_REG_FRC_SYS_CLK    0x1d62
#define    RTL8367D_SYSCLK_FRC_MD_OFFSET    2
#define    RTL8367D_SYSCLK_FRC_MD_MASK    0x4
#define    RTL8367D_SYSCLK_FRC_VAL_OFFSET    0
#define    RTL8367D_SYSCLK_FRC_VAL_MASK    0x3

#define    RTL8367D_REG_AFE_SSC_CTRL    0x1d63
#define    RTL8367D_PH_RSTB_TXD1_OFFSET    9
#define    RTL8367D_PH_RSTB_TXD1_MASK    0x200
#define    RTL8367D_PH_RSTB_TXC1_OFFSET    8
#define    RTL8367D_PH_RSTB_TXC1_MASK    0x100
#define    RTL8367D_PH_RSTB_TXD0_OFFSET    7
#define    RTL8367D_PH_RSTB_TXD0_MASK    0x80
#define    RTL8367D_PH_RSTB_TXC0_OFFSET    6
#define    RTL8367D_PH_RSTB_TXC0_MASK    0x40
#define    RTL8367D_PH_RSTBSYS_OFFSET    5
#define    RTL8367D_PH_RSTBSYS_MASK    0x20
#define    RTL8367D_PH_RSTB8051_OFFSET    4
#define    RTL8367D_PH_RSTB8051_MASK    0x10
#define    RTL8367D_OREG_SSC_OFFSET    0
#define    RTL8367D_OREG_SSC_MASK    0xF

#define    RTL8367D_REG_BUFF_RST_CTRL0    0x1d64
#define    RTL8367D_BUFFRST_TXESD_EN_OFFSET    13
#define    RTL8367D_BUFFRST_TXESD_EN_MASK    0x2000
#define    RTL8367D_BUFF_RST_TIME_LONG_OFFSET    8
#define    RTL8367D_BUFF_RST_TIME_LONG_MASK    0x1F00
#define    RTL8367D_BUFF_RST_TIME_SHORT_OFFSET    3
#define    RTL8367D_BUFF_RST_TIME_SHORT_MASK    0xF8
#define    RTL8367D_SW_BUFF_RST_OFFSET    2
#define    RTL8367D_SW_BUFF_RST_MASK    0x4
#define    RTL8367D_IMS_BUFF_RST_OFFSET    1
#define    RTL8367D_IMS_BUFF_RST_MASK    0x2
#define    RTL8367D_IMR_BUFF_RST_OFFSET    0
#define    RTL8367D_IMR_BUFF_RST_MASK    0x1

#define    RTL8367D_REG_BUFF_RST_CTRL1    0x1d65
#define    RTL8367D_BUFFRST_SYSOVER_EN_OFFSET    11
#define    RTL8367D_BUFFRST_SYSOVER_EN_MASK    0x800
#define    RTL8367D_BUFFRST_SYSOVER_THR_OFFSET    0
#define    RTL8367D_BUFFRST_SYSOVER_THR_MASK    0x7FF

#define    RTL8367D_REG_BUFF_RST_CTRL2    0x1d66
#define    RTL8367D_BUFFRST_QOVER_EN_OFFSET    11
#define    RTL8367D_BUFFRST_QOVER_EN_MASK    0x800
#define    RTL8367D_BUFFRST_QOVER_THR_OFFSET    0
#define    RTL8367D_BUFFRST_QOVER_THR_MASK    0x7FF

#define    RTL8367D_REG_BUFF_RST_CTRL3    0x1d67
#define    RTL8367D_DSC_TIMER_OFFSET    12
#define    RTL8367D_DSC_TIMER_MASK    0xF000
#define    RTL8367D_BUFFRST_DSCOVER_THR_OFFSET    1
#define    RTL8367D_BUFFRST_DSCOVER_THR_MASK    0xFFE
#define    RTL8367D_BUFFRST_DSCOVER_EN_OFFSET    0
#define    RTL8367D_BUFFRST_DSCOVER_EN_MASK    0x1

#define    RTL8367D_REG_BUFF_RST_CTRL4    0x1d68
#define    RTL8367D_INDSC_TIMER_OFFSET    12
#define    RTL8367D_INDSC_TIMER_MASK    0xF000
#define    RTL8367D_BUFFRST_INDSCOVER_THR_OFFSET    1
#define    RTL8367D_BUFFRST_INDSCOVER_THR_MASK    0xFFE
#define    RTL8367D_BUFFRST_INDSCOVER_EN_OFFSET    0
#define    RTL8367D_BUFFRST_INDSCOVER_EN_MASK    0x1

#define    RTL8367D_REG_TOP_CON0    0x1d70
#define    RTL8367D_MAC7_SEL_EXT1_OFFSET    13
#define    RTL8367D_MAC7_SEL_EXT1_MASK    0x2000
#define    RTL8367D_MAC4_SEL_EXT1_OFFSET    12
#define    RTL8367D_MAC4_SEL_EXT1_MASK    0x1000
#define    RTL8367D_FIB_EEE_AB_OFFSET    11
#define    RTL8367D_FIB_EEE_AB_MASK    0x800
#define    RTL8367D_ADCCKIEN_OFFSET    10
#define    RTL8367D_ADCCKIEN_MASK    0x400
#define    RTL8367D_OCP_TIMEOUT_OFFSET    5
#define    RTL8367D_OCP_TIMEOUT_MASK    0x3E0
#define    RTL8367D_RG2_TXC_SEL_OFFSET    3
#define    RTL8367D_RG2_TXC_SEL_MASK    0x8
#define    RTL8367D_RG1TXC_SEL_OFFSET    2
#define    RTL8367D_RG1TXC_SEL_MASK    0x4
#define    RTL8367D_SYNC_1588_EN_OFFSET    1
#define    RTL8367D_SYNC_1588_EN_MASK    0x2
#define    RTL8367D_LS_MODE_OFFSET    0
#define    RTL8367D_LS_MODE_MASK    0x1

#define    RTL8367D_REG_TOP_CON1    0x1d71
#define    RTL8367D_TA_CHK_EN_OFFSET    2
#define    RTL8367D_TA_CHK_EN_MASK    0x4
#define    RTL8367D_SLV_EG_SEL_OFFSET    1
#define    RTL8367D_SLV_EG_SEL_MASK    0x2
#define    RTL8367D_IIC_OP_DRAIN_OFFSET    0
#define    RTL8367D_IIC_OP_DRAIN_MASK    0x1

#define    RTL8367D_REG_SWR_FPWM    0x1d72
#define    RTL8367D_SWR_FPWM_OFFSET    0
#define    RTL8367D_SWR_FPWM_MASK    0x1

#define    RTL8367D_REG_EEEP_CTRL_500M    0x1d73

#define    RTL8367D_REG_SHORT_PRMB    0x1d74
#define    RTL8367D_SHORT_PRMB_OFFSET    0
#define    RTL8367D_SHORT_PRMB_MASK    0x1

#define    RTL8367D_REG_TOP_ACS_OPT    0x1d75
#define    RTL8367D_CFG_OCP_DIRACS_OFFSET    1
#define    RTL8367D_CFG_OCP_DIRACS_MASK    0x2
#define    RTL8367D_CFG_67D_DIR_MDX_OFFSET    0
#define    RTL8367D_CFG_67D_DIR_MDX_MASK    0x1

#define    RTL8367D_REG_CAL_CMD_0    0x1d76
#define    RTL8367D_CAL_CME_EN_OFFSET    5
#define    RTL8367D_CAL_CME_EN_MASK    0x20
#define    RTL8367D_CAL_PHYAD_OFFSET    0
#define    RTL8367D_CAL_PHYAD_MASK    0x1F

#define    RTL8367D_REG_CAL_CMD_1    0x1d77
#define    RTL8367D_CAL_CMD7_OFFSET    6
#define    RTL8367D_CAL_CMD7_MASK    0x40
#define    RTL8367D_CAL_CMD6_OFFSET    5
#define    RTL8367D_CAL_CMD6_MASK    0x20
#define    RTL8367D_CAL_CMD5_OFFSET    4
#define    RTL8367D_CAL_CMD5_MASK    0x10
#define    RTL8367D_CAL_CMD4_OFFSET    3
#define    RTL8367D_CAL_CMD4_MASK    0x8
#define    RTL8367D_CAL_CMD3_OFFSET    2
#define    RTL8367D_CAL_CMD3_MASK    0x4
#define    RTL8367D_CAL_CMD2_OFFSET    1
#define    RTL8367D_CAL_CMD2_MASK    0x2
#define    RTL8367D_CAL_CMD1_OFFSET    0
#define    RTL8367D_CAL_CMD1_MASK    0x1

#define    RTL8367D_REG_SDS1_MISC0    0x1d78
#define    RTL8367D_PA33PC_EN_S1_OFFSET    10
#define    RTL8367D_PA33PC_EN_S1_MASK    0x400
#define    RTL8367D_PA12PC_EN_S1_OFFSET    9
#define    RTL8367D_PA12PC_EN_S1_MASK    0x200
#define    RTL8367D_SDS1_MISC0_SDS_PWR_ISO_EN_1_OFFSET    8
#define    RTL8367D_SDS1_MISC0_SDS_PWR_ISO_EN_1_MASK    0x100
#define    RTL8367D_SDS1_MISC0_SDS_FRC_REG4_EN_1_OFFSET    7
#define    RTL8367D_SDS1_MISC0_SDS_FRC_REG4_EN_1_MASK    0x80
#define    RTL8367D_SDS1_MISC0_SDS_FRC_REG4_FIB100_1_OFFSET    6
#define    RTL8367D_SDS1_MISC0_SDS_FRC_REG4_FIB100_1_MASK    0x40
#define    RTL8367D_SDS1_MISC0_CFG_UNIDIR_TX_OFFSET    5
#define    RTL8367D_SDS1_MISC0_CFG_UNIDIR_TX_MASK    0x20
#define    RTL8367D_SDS1_MODE_OFFSET    0
#define    RTL8367D_SDS1_MODE_MASK    0x1F

#define    RTL8367D_REG_SRAM_CTRL_MISC0    0x1d7a
#define    RTL8367D_FRC_HSARAM_TGL_OFFSET    15
#define    RTL8367D_FRC_HSARAM_TGL_MASK    0x8000
#define    RTL8367D_BIST_GRP_EN_OUTQRAM_OFFSET    8
#define    RTL8367D_BIST_GRP_EN_OUTQRAM_MASK    0x7F00
#define    RTL8367D_TEST1_HTRAM_OFFSET    7
#define    RTL8367D_TEST1_HTRAM_MASK    0x80
#define    RTL8367D_TESTRWM_HTRAM_OFFSET    6
#define    RTL8367D_TESTRWM_HTRAM_MASK    0x40
#define    RTL8367D_DYN_READ_EN_HSARAM_OFFSET    5
#define    RTL8367D_DYN_READ_EN_HSARAM_MASK    0x20
#define    RTL8367D_DYN_READ_EN_OUTQRAM_OFFSET    4
#define    RTL8367D_DYN_READ_EN_OUTQRAM_MASK    0x10
#define    RTL8367D_DYN_READ_EN_HTRAM_OFFSET    3
#define    RTL8367D_DYN_READ_EN_HTRAM_MASK    0x8
#define    RTL8367D_BIST_LOOP_MODE_HSARAM_OFFSET    2
#define    RTL8367D_BIST_LOOP_MODE_HSARAM_MASK    0x4
#define    RTL8367D_BIST_LOOP_MODE_OUTQRAM_OFFSET    1
#define    RTL8367D_BIST_LOOP_MODE_OUTQRAM_MASK    0x2
#define    RTL8367D_BIST_LOOP_MODE_HTRAM_OFFSET    0
#define    RTL8367D_BIST_LOOP_MODE_HTRAM_MASK    0x1

#define    RTL8367D_REG_EF_NRAM_WR_CMD0    0x1d7b

#define    RTL8367D_REG_EF_NRAM_WR_CMD1    0x1d7c

#define    RTL8367D_REG_EF_NRAM_WR_CMD2    0x1d7d

#define    RTL8367D_REG_EF_NRAM_ADR_BGN    0x1d7e
#define    RTL8367D_EF_NRAM_ADR_BGN_EFUSE_CHK_PS_OFFSET    8
#define    RTL8367D_EF_NRAM_ADR_BGN_EFUSE_CHK_PS_MASK    0x100
#define    RTL8367D_NRAM_ADR_BGN_OFFSET    0
#define    RTL8367D_NRAM_ADR_BGN_MASK    0xFF

#define    RTL8367D_REG_EFUSE_CHK_CMD0    0x1d7f
#define    RTL8367D_EF_CHK_BGN_OFFSET    8
#define    RTL8367D_EF_CHK_BGN_MASK    0xFF00
#define    RTL8367D_EF_CHK_END_OFFSET    0
#define    RTL8367D_EF_CHK_END_MASK    0xFF

#define    RTL8367D_REG_EFUSE_CHK_CMD1    0x1d80

#define    RTL8367D_REG_TOP_CON_MISC0    0x1d81
#define    RTL8367D_DBG_SEL_SDS01_OFFSET    4
#define    RTL8367D_DBG_SEL_SDS01_MASK    0x10
#define    RTL8367D_PERI_WRMSK_EN_OFFSET    0
#define    RTL8367D_PERI_WRMSK_EN_MASK    0xF

#define    RTL8367D_REG_DSS_0_CTRL0    0x1d82
#define    RTL8367D_DSS_0_RO_SEL_OFFSET    7
#define    RTL8367D_DSS_0_RO_SEL_MASK    0x380
#define    RTL8367D_DSS_0_WIRE_SEL_OFFSET    6
#define    RTL8367D_DSS_0_WIRE_SEL_MASK    0x40
#define    RTL8367D_DSS_0_RST_N_OFFSET    5
#define    RTL8367D_DSS_0_RST_N_MASK    0x20
#define    RTL8367D_DSS_0_SPEED_EN_OFFSET    4
#define    RTL8367D_DSS_0_SPEED_EN_MASK    0x10
#define    RTL8367D_DSS_0_DATA_IN_19_16_OFFSET    0
#define    RTL8367D_DSS_0_DATA_IN_19_16_MASK    0xF

#define    RTL8367D_REG_DSS_0_CTRL1    0x1d83

#define    RTL8367D_REG_DSS_0_STS0    0x1d84
#define    RTL8367D_DSS_0_WSORT_GO_OFFSET    5
#define    RTL8367D_DSS_0_WSORT_GO_MASK    0x20
#define    RTL8367D_DSS_0_READY_OFFSET    4
#define    RTL8367D_DSS_0_READY_MASK    0x10
#define    RTL8367D_DSS_0_COUNT_OUT_19_16_OFFSET    0
#define    RTL8367D_DSS_0_COUNT_OUT_19_16_MASK    0xF

#define    RTL8367D_REG_DSS_0_STS1    0x1d85

#define    RTL8367D_REG_DSS_1_CTRL0    0x1d86
#define    RTL8367D_DSS_1_RO_SEL_OFFSET    7
#define    RTL8367D_DSS_1_RO_SEL_MASK    0x380
#define    RTL8367D_DSS_1_WIRE_SEL_OFFSET    6
#define    RTL8367D_DSS_1_WIRE_SEL_MASK    0x40
#define    RTL8367D_DSS_1_RST_N_OFFSET    5
#define    RTL8367D_DSS_1_RST_N_MASK    0x20
#define    RTL8367D_DSS_1_SPEED_EN_OFFSET    4
#define    RTL8367D_DSS_1_SPEED_EN_MASK    0x10
#define    RTL8367D_DSS_1_DATA_IN_19_16_OFFSET    0
#define    RTL8367D_DSS_1_DATA_IN_19_16_MASK    0xF

#define    RTL8367D_REG_DSS_1_CTRL1    0x1d87

#define    RTL8367D_REG_DSS_1_STS0    0x1d88
#define    RTL8367D_DSS_1_WSORT_GO_OFFSET    5
#define    RTL8367D_DSS_1_WSORT_GO_MASK    0x20
#define    RTL8367D_DSS_1_READY_OFFSET    4
#define    RTL8367D_DSS_1_READY_MASK    0x10
#define    RTL8367D_DSS_1_COUNT_OUT_19_16_OFFSET    0
#define    RTL8367D_DSS_1_COUNT_OUT_19_16_MASK    0xF

#define    RTL8367D_REG_DSS_1_STS1    0x1d89

#define    RTL8367D_REG_DSS_2_CTRL0    0x1d8a
#define    RTL8367D_DSS_2_RO_SEL_OFFSET    7
#define    RTL8367D_DSS_2_RO_SEL_MASK    0x380
#define    RTL8367D_DSS_2_WIRE_SEL_OFFSET    6
#define    RTL8367D_DSS_2_WIRE_SEL_MASK    0x40
#define    RTL8367D_DSS_2_RST_N_OFFSET    5
#define    RTL8367D_DSS_2_RST_N_MASK    0x20
#define    RTL8367D_DSS_2_SPEED_EN_OFFSET    4
#define    RTL8367D_DSS_2_SPEED_EN_MASK    0x10
#define    RTL8367D_DSS_2_DATA_IN_19_16_OFFSET    0
#define    RTL8367D_DSS_2_DATA_IN_19_16_MASK    0xF

#define    RTL8367D_REG_DSS_2_CTRL1    0x1d8b

#define    RTL8367D_REG_DSS_2_STS0    0x1d8c
#define    RTL8367D_DSS_2_WSORT_GO_OFFSET    5
#define    RTL8367D_DSS_2_WSORT_GO_MASK    0x20
#define    RTL8367D_DSS_2_READY_OFFSET    4
#define    RTL8367D_DSS_2_READY_MASK    0x10
#define    RTL8367D_DSS_2_COUNT_OUT_19_16_OFFSET    0
#define    RTL8367D_DSS_2_COUNT_OUT_19_16_MASK    0xF

#define    RTL8367D_REG_DSS_2_STS1    0x1d8d

#define    RTL8367D_REG_THERMAL_CTRL_0    0x1d90
#define    RTL8367D_TM_REG_TD_WREP_SEL_OFFSET    14
#define    RTL8367D_TM_REG_TD_WREP_SEL_MASK    0x4000
#define    RTL8367D_TM_REG_PPOW_OFFSET    13
#define    RTL8367D_TM_REG_PPOW_MASK    0x2000
#define    RTL8367D_TM_REG_RSTB_OFFSET    12
#define    RTL8367D_TM_REG_RSTB_MASK    0x1000
#define    RTL8367D_TM_REG_BIASCHOP_OFFSET    11
#define    RTL8367D_TM_REG_BIASCHOP_MASK    0x800
#define    RTL8367D_TM_REG_CHOPEN_OFFSET    10
#define    RTL8367D_TM_REG_CHOPEN_MASK    0x400
#define    RTL8367D_TM_REG_CAL_EN_OFFSET    9
#define    RTL8367D_TM_REG_CAL_EN_MASK    0x200
#define    RTL8367D_TM_REG_HOLD_EN_OFFSET    8
#define    RTL8367D_TM_REG_HOLD_EN_MASK    0x100
#define    RTL8367D_TM_REG_CKSOURCESEL_OFFSET    7
#define    RTL8367D_TM_REG_CKSOURCESEL_MASK    0x80
#define    RTL8367D_TM_REG_BIASDEM_SEL_OFFSET    6
#define    RTL8367D_TM_REG_BIASDEM_SEL_MASK    0x40
#define    RTL8367D_TM_REG_CHOPFREQSEL_OFFSET    2
#define    RTL8367D_TM_REG_CHOPFREQSEL_MASK    0x3C
#define    RTL8367D_TM_REG_HOLD_DLY_OFFSET    0
#define    RTL8367D_TM_REG_HOLD_DLY_MASK    0x3

#define    RTL8367D_REG_THERMAL_CTRL_1    0x1d91
#define    RTL8367D_TM_REG_FILTEREDGESEL_OFFSET    15
#define    RTL8367D_TM_REG_FILTEREDGESEL_MASK    0x8000
#define    RTL8367D_TM_REG_ORDER3_OFFSET    14
#define    RTL8367D_TM_REG_ORDER3_MASK    0x4000
#define    RTL8367D_TM_REG_OPCURSEL_OFFSET    12
#define    RTL8367D_TM_REG_OPCURSEL_MASK    0x3000
#define    RTL8367D_TM_REG_OSCCURSEL_OFFSET    10
#define    RTL8367D_TM_REG_OSCCURSEL_MASK    0xC00
#define    RTL8367D_TM_REG_VBE_BIASSEL_OFFSET    8
#define    RTL8367D_TM_REG_VBE_BIASSEL_MASK    0x300
#define    RTL8367D_TM_REG_ADCCKSEL_OFFSET    5
#define    RTL8367D_TM_REG_ADCCKSEL_MASK    0xE0
#define    RTL8367D_TM_REG_DSR_OFFSET    2
#define    RTL8367D_TM_REG_DSR_MASK    0x1C
#define    RTL8367D_TM_REG_RESOL_OFFSET    0
#define    RTL8367D_TM_REG_RESOL_MASK    0x3

#define    RTL8367D_REG_THERMAL_CTRL_2    0x1d92
#define    RTL8367D_THERMAL_CTRL_2_OFFSET    0
#define    RTL8367D_THERMAL_CTRL_2_MASK    0x3F

#define    RTL8367D_REG_THERMAL_CTRL_3    0x1d93

#define    RTL8367D_REG_THERMAL_CTRL_4    0x1d94
#define    RTL8367D_THERMAL_CTRL_4_OFFSET    0
#define    RTL8367D_THERMAL_CTRL_4_MASK    0x3F

#define    RTL8367D_REG_THERMAL_CTRL_5    0x1d95

#define    RTL8367D_REG_THERMAL_CTRL_6    0x1d96
#define    RTL8367D_THERMAL_CTRL_6_OFFSET    0
#define    RTL8367D_THERMAL_CTRL_6_MASK    0x7F

#define    RTL8367D_REG_THERMAL_CTRL_7    0x1d97

#define    RTL8367D_REG_THERMAL_CTRL_8    0x1d98
#define    RTL8367D_THERMAL_CTRL_8_OFFSET    0
#define    RTL8367D_THERMAL_CTRL_8_MASK    0xFF

#define    RTL8367D_REG_THERMAL_CTRL_9    0x1d99

#define    RTL8367D_REG_THERMAL_CTRL_10    0x1d9a
#define    RTL8367D_THERMAL_CTRL_10_OFFSET    0
#define    RTL8367D_THERMAL_CTRL_10_MASK    0x1FFF

#define    RTL8367D_REG_THERMAL_CTRL_11    0x1d9b

#define    RTL8367D_REG_THERMAL_CTRL_12    0x1d9c
#define    RTL8367D_TM_CMP_HIGH_EN0_OFFSET    3
#define    RTL8367D_TM_CMP_HIGH_EN0_MASK    0x8
#define    RTL8367D_TM_HIGH_THR0_18_16_OFFSET    0
#define    RTL8367D_TM_HIGH_THR0_18_16_MASK    0x7

#define    RTL8367D_REG_THERMAL_CTRL_13    0x1d9d

#define    RTL8367D_REG_THERMAL_CTRL_14    0x1d9e
#define    RTL8367D_TM_CMP_LOW_EN0_OFFSET    3
#define    RTL8367D_TM_CMP_LOW_EN0_MASK    0x8
#define    RTL8367D_TM_LOW_THR0_18_16_OFFSET    0
#define    RTL8367D_TM_LOW_THR0_18_16_MASK    0x7

#define    RTL8367D_REG_THERMAL_CTRL_15    0x1d9f

#define    RTL8367D_REG_THERMAL_CTRL_16    0x1da0
#define    RTL8367D_TM_CMP_HIGH_EN1_OFFSET    3
#define    RTL8367D_TM_CMP_HIGH_EN1_MASK    0x8
#define    RTL8367D_TM_HIGH_THR1_18_16_OFFSET    0
#define    RTL8367D_TM_HIGH_THR1_18_16_MASK    0x7

#define    RTL8367D_REG_THERMAL_CTRL_17    0x1da1

#define    RTL8367D_REG_THERMAL_CTRL_18    0x1da2
#define    RTL8367D_TM_CMP_LOW_EN1_OFFSET    3
#define    RTL8367D_TM_CMP_LOW_EN1_MASK    0x8
#define    RTL8367D_TM_LOW_THR1_18_16_OFFSET    0
#define    RTL8367D_TM_LOW_THR1_18_16_MASK    0x7

#define    RTL8367D_REG_THERMAL_CTRL_19    0x1da3

#define    RTL8367D_REG_THERMAL_STS_0    0x1da4
#define    RTL8367D_TM_SAMPLE_TOG_OFFSET    3
#define    RTL8367D_TM_SAMPLE_TOG_MASK    0x8
#define    RTL8367D_TM_SENS_OUT_18_16_OFFSET    0
#define    RTL8367D_TM_SENS_OUT_18_16_MASK    0x7

#define    RTL8367D_REG_THERMAL_STS_1    0x1da5

#define    RTL8367D_REG_THERMAL_STS_2    0x1da6
#define    RTL8367D_THERMAL_STS_2_OFFSET    0
#define    RTL8367D_THERMAL_STS_2_MASK    0x3F

#define    RTL8367D_REG_THERMAL_STS_3    0x1da7

#define    RTL8367D_REG_THERMAL_STS_4    0x1da8
#define    RTL8367D_CLR_TM_TEMP_MAX_OFFSET    3
#define    RTL8367D_CLR_TM_TEMP_MAX_MASK    0x8
#define    RTL8367D_TM_TEMP_MAX_18_16_OFFSET    0
#define    RTL8367D_TM_TEMP_MAX_18_16_MASK    0x7

#define    RTL8367D_REG_THERMAL_STS_5    0x1da9

#define    RTL8367D_REG_THERMAL_STS_6    0x1daa
#define    RTL8367D_CLR_TM_TEMP_MIN_OFFSET    3
#define    RTL8367D_CLR_TM_TEMP_MIN_MASK    0x8
#define    RTL8367D_TM_TEMP_MIN_18_16_OFFSET    0
#define    RTL8367D_TM_TEMP_MIN_18_16_MASK    0x7

#define    RTL8367D_REG_THERMAL_STS_7    0x1dab

#define    RTL8367D_REG_THERMAL_STS_8    0x1dac
#define    RTL8367D_PWRON_ADC_RDY_OFFSET    6
#define    RTL8367D_PWRON_ADC_RDY_MASK    0x40
#define    RTL8367D_PWRON_ADC_OUT_21_16_OFFSET    0
#define    RTL8367D_PWRON_ADC_OUT_21_16_MASK    0x3F

#define    RTL8367D_REG_THERMAL_STS_9    0x1dad

#define    RTL8367D_REG_CFG_GPIO_SRC_X0    0x1db0

#define    RTL8367D_REG_CFG_GPIO_SRC_X1    0x1db1

#define    RTL8367D_REG_CFG_GPIO_SRC_X2    0x1db2

#define    RTL8367D_REG_CFG_GPIO_SRC_X3    0x1db3
#define    RTL8367D_CFG_GPIO_SRC_X3_OFFSET    0
#define    RTL8367D_CFG_GPIO_SRC_X3_MASK    0x3FFF

#define    RTL8367D_REG_GPIO_8051_O_X0    0x1db4

#define    RTL8367D_REG_GPIO_8051_O_X1    0x1db5

#define    RTL8367D_REG_GPIO_8051_O_X2    0x1db6

#define    RTL8367D_REG_GPIO_8051_O_X3    0x1db7
#define    RTL8367D_GPIO_8051_O_X3_OFFSET    0
#define    RTL8367D_GPIO_8051_O_X3_MASK    0x3FFF

#define    RTL8367D_REG_GPIO_8051_OE_X0    0x1db8

#define    RTL8367D_REG_GPIO_8051_OE_X1    0x1db9

#define    RTL8367D_REG_GPIO_8051_OE_X2    0x1dba

#define    RTL8367D_REG_GPIO_8051_OE_X3    0x1dbb
#define    RTL8367D_GPIO_8051_OE_X3_OFFSET    0
#define    RTL8367D_GPIO_8051_OE_X3_MASK    0x3FFF

#define    RTL8367D_REG_CFG_CHIP_67D_DUMMY0    0x1df0

#define    RTL8367D_REG_CFG_CHIP_67D_DUMMY1    0x1df1

#define    RTL8367D_REG_CFG_CHIP_67D_DUMMY2    0x1df2

#define    RTL8367D_REG_CFG_CHIP_67D_DUMMY3    0x1df3

#define    RTL8367D_REG_CFG_CHIP_67D_DUMMY4    0x1df4

#define    RTL8367D_REG_BOND_FOR_READ    0x1df5
#define    RTL8367D_BOND_FOR_READ_OFFSET    0
#define    RTL8367D_BOND_FOR_READ_MASK    0x7FF

/* (16'h1e00)phy_reg */

#define    RTL8367D_REG_PHY_RG0X_CEN    0x1e00

#define    RTL8367D_REG_PHY_RG1X_CEN    0x1e01

#define    RTL8367D_REG_PHY_RG2X_CEN    0x1e02

#define    RTL8367D_REG_PHY_RG3X_CEN    0x1e03

#define    RTL8367D_REG_PHY_RG4X_CEN    0x1e04

#define    RTL8367D_REG_PHY_RG5X_CEN    0x1e05

#define    RTL8367D_REG_PHY_RG6X_CEN    0x1e06

#define    RTL8367D_REG_PHY_RG7X_CEN    0x1e07

#define    RTL8367D_REG_PHY_RG8X_CEN    0x1e08

#define    RTL8367D_REG_PHY_RG9X_CEN    0x1e09

#define    RTL8367D_REG_PHY_RG10X_CEN    0x1e0a

#define    RTL8367D_REG_PHY_RG11X_CEN    0x1e0b

#define    RTL8367D_REG_PHY_RG12X_CEN    0x1e0c

#define    RTL8367D_REG_PHY_RG13X_CEN    0x1e0d

#define    RTL8367D_REG_PHY_RG0X_PLL    0x1e0e

#define    RTL8367D_REG_PHY_RG1X_PLL    0x1e0f

#define    RTL8367D_REG_PHY_RG2X_PLL    0x1e10

#define    RTL8367D_REG_PHY_RG3X_PLL    0x1e11

#define    RTL8367D_REG_PHY_RG4X_PLL    0x1e12

#define    RTL8367D_REG_PHY_RG5X_PLL    0x1e13

#define    RTL8367D_REG_PHY_RG6X_PLL    0x1e14

#define    RTL8367D_REG_PHY_RG7X_PLL    0x1e15

#define    RTL8367D_REG_PHY_RG8X_PLL    0x1e16

#define    RTL8367D_REG_PHY_RG9X_PLL    0x1e17

#define    RTL8367D_REG_PHY_POW_PLL    0x1e18
#define    RTL8367D_ADCCKI_EN_OFFSET    2
#define    RTL8367D_ADCCKI_EN_MASK    0xC
#define    RTL8367D_POWLDO_PLL_OFFSET    1
#define    RTL8367D_POWLDO_PLL_MASK    0x2
#define    RTL8367D_POWSW_PLL_OFFSET    0
#define    RTL8367D_POWSW_PLL_MASK    0x1

#define    RTL8367D_REG_PHY_IB_DN_10M_X0    0x1e19
#define    RTL8367D_CFG_IB_ENDN_10M_X0_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_10M_X0_MASK    0x100
#define    RTL8367D_CFG_IB_DN_10M_X0_OFFSET    0
#define    RTL8367D_CFG_IB_DN_10M_X0_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_10M_X0    0x1e1a
#define    RTL8367D_CFG_IB_UPALL_10M_X0_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_10M_X0_MASK    0x100
#define    RTL8367D_CFG_IB_UP_10M_X0_OFFSET    0
#define    RTL8367D_CFG_IB_UP_10M_X0_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_100M_X0    0x1e1b
#define    RTL8367D_CFG_IB_ENDN_100M_X0_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_100M_X0_MASK    0x100
#define    RTL8367D_CFG_IB_DN_100M_X0_OFFSET    0
#define    RTL8367D_CFG_IB_DN_100M_X0_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_100M_X0    0x1e1c
#define    RTL8367D_CFG_IB_UPALL_100M_X0_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_100M_X0_MASK    0x100
#define    RTL8367D_CFG_IB_UP_100M_X0_OFFSET    0
#define    RTL8367D_CFG_IB_UP_100M_X0_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_1000M_X0    0x1e1d
#define    RTL8367D_CFG_IB_ENDN_1000M_X0_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_1000M_X0_MASK    0x100
#define    RTL8367D_CFG_IB_DN_1000M_X0_OFFSET    0
#define    RTL8367D_CFG_IB_DN_1000M_X0_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_1000M_X0    0x1e1e
#define    RTL8367D_CFG_IB_UPALL_1000M_X0_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_1000M_X0_MASK    0x100
#define    RTL8367D_CFG_IB_UP_1000M_X0_OFFSET    0
#define    RTL8367D_CFG_IB_UP_1000M_X0_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_10M_X1    0x1e1f
#define    RTL8367D_CFG_IB_ENDN_10M_X1_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_10M_X1_MASK    0x100
#define    RTL8367D_CFG_IB_DN_10M_X1_OFFSET    0
#define    RTL8367D_CFG_IB_DN_10M_X1_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_10M_X1    0x1e20
#define    RTL8367D_CFG_IB_UPALL_10M_X1_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_10M_X1_MASK    0x100
#define    RTL8367D_CFG_IB_UP_10M_X1_OFFSET    0
#define    RTL8367D_CFG_IB_UP_10M_X1_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_100M_X1    0x1e21
#define    RTL8367D_CFG_IB_ENDN_100M_X1_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_100M_X1_MASK    0x100
#define    RTL8367D_CFG_IB_DN_100M_X1_OFFSET    0
#define    RTL8367D_CFG_IB_DN_100M_X1_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_100M_X1    0x1e22
#define    RTL8367D_CFG_IB_UPALL_100M_X1_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_100M_X1_MASK    0x100
#define    RTL8367D_CFG_IB_UP_100M_X1_OFFSET    0
#define    RTL8367D_CFG_IB_UP_100M_X1_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_1000M_X1    0x1e23
#define    RTL8367D_CFG_IB_ENDN_1000M_X1_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_1000M_X1_MASK    0x100
#define    RTL8367D_CFG_IB_DN_1000M_X1_OFFSET    0
#define    RTL8367D_CFG_IB_DN_1000M_X1_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_1000M_X1    0x1e24
#define    RTL8367D_CFG_IB_UPALL_1000M_X1_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_1000M_X1_MASK    0x100
#define    RTL8367D_CFG_IB_UP_1000M_X1_OFFSET    0
#define    RTL8367D_CFG_IB_UP_1000M_X1_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_10M_X2    0x1e25
#define    RTL8367D_CFG_IB_ENDN_10M_X2_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_10M_X2_MASK    0x100
#define    RTL8367D_CFG_IB_DN_10M_X2_OFFSET    0
#define    RTL8367D_CFG_IB_DN_10M_X2_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_10M_X2    0x1e26
#define    RTL8367D_CFG_IB_UPALL_10M_X2_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_10M_X2_MASK    0x100
#define    RTL8367D_CFG_IB_UP_10M_X2_OFFSET    0
#define    RTL8367D_CFG_IB_UP_10M_X2_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_100M_X2    0x1e27
#define    RTL8367D_CFG_IB_ENDN_100M_X2_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_100M_X2_MASK    0x100
#define    RTL8367D_CFG_IB_DN_100M_X2_OFFSET    0
#define    RTL8367D_CFG_IB_DN_100M_X2_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_100M_X2    0x1e28
#define    RTL8367D_CFG_IB_UPALL_100M_X2_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_100M_X2_MASK    0x100
#define    RTL8367D_CFG_IB_UP_100M_X2_OFFSET    0
#define    RTL8367D_CFG_IB_UP_100M_X2_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_1000M_X2    0x1e29
#define    RTL8367D_CFG_IB_ENDN_1000M_X2_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_1000M_X2_MASK    0x100
#define    RTL8367D_CFG_IB_DN_1000M_X2_OFFSET    0
#define    RTL8367D_CFG_IB_DN_1000M_X2_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_1000M_X2    0x1e2a
#define    RTL8367D_CFG_IB_UPALL_1000M_X2_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_1000M_X2_MASK    0x100
#define    RTL8367D_CFG_IB_UP_1000M_X2_OFFSET    0
#define    RTL8367D_CFG_IB_UP_1000M_X2_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_10M_X3    0x1e2b
#define    RTL8367D_CFG_IB_ENDN_10M_X3_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_10M_X3_MASK    0x100
#define    RTL8367D_CFG_IB_DN_10M_X3_OFFSET    0
#define    RTL8367D_CFG_IB_DN_10M_X3_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_10M_X3    0x1e2c
#define    RTL8367D_CFG_IB_UPALL_10M_X3_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_10M_X3_MASK    0x100
#define    RTL8367D_CFG_IB_UP_10M_X3_OFFSET    0
#define    RTL8367D_CFG_IB_UP_10M_X3_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_100M_X3    0x1e2d
#define    RTL8367D_CFG_IB_ENDN_100M_X3_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_100M_X3_MASK    0x100
#define    RTL8367D_CFG_IB_DN_100M_X3_OFFSET    0
#define    RTL8367D_CFG_IB_DN_100M_X3_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_100M_X3    0x1e2e
#define    RTL8367D_CFG_IB_UPALL_100M_X3_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_100M_X3_MASK    0x100
#define    RTL8367D_CFG_IB_UP_100M_X3_OFFSET    0
#define    RTL8367D_CFG_IB_UP_100M_X3_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_1000M_X3    0x1e2f
#define    RTL8367D_CFG_IB_ENDN_1000M_X3_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_1000M_X3_MASK    0x100
#define    RTL8367D_CFG_IB_DN_1000M_X3_OFFSET    0
#define    RTL8367D_CFG_IB_DN_1000M_X3_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_1000M_X3    0x1e30
#define    RTL8367D_CFG_IB_UPALL_1000M_X3_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_1000M_X3_MASK    0x100
#define    RTL8367D_CFG_IB_UP_1000M_X3_OFFSET    0
#define    RTL8367D_CFG_IB_UP_1000M_X3_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_10M_X4    0x1e31
#define    RTL8367D_CFG_IB_ENDN_10M_X4_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_10M_X4_MASK    0x100
#define    RTL8367D_CFG_IB_DN_10M_X4_OFFSET    0
#define    RTL8367D_CFG_IB_DN_10M_X4_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_10M_X4    0x1e32
#define    RTL8367D_CFG_IB_UPALL_10M_X4_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_10M_X4_MASK    0x100
#define    RTL8367D_CFG_IB_UP_10M_X4_OFFSET    0
#define    RTL8367D_CFG_IB_UP_10M_X4_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_100M_X4    0x1e33
#define    RTL8367D_CFG_IB_ENDN_100M_X4_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_100M_X4_MASK    0x100
#define    RTL8367D_CFG_IB_DN_100M_X4_OFFSET    0
#define    RTL8367D_CFG_IB_DN_100M_X4_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_100M_X4    0x1e34
#define    RTL8367D_CFG_IB_UPALL_100M_X4_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_100M_X4_MASK    0x100
#define    RTL8367D_CFG_IB_UP_100M_X4_OFFSET    0
#define    RTL8367D_CFG_IB_UP_100M_X4_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_DN_1000M_X4    0x1e35
#define    RTL8367D_CFG_IB_ENDN_1000M_X4_OFFSET    8
#define    RTL8367D_CFG_IB_ENDN_1000M_X4_MASK    0x100
#define    RTL8367D_CFG_IB_DN_1000M_X4_OFFSET    0
#define    RTL8367D_CFG_IB_DN_1000M_X4_MASK    0xFF

#define    RTL8367D_REG_PHY_IB_UP_1000M_X4    0x1e36
#define    RTL8367D_CFG_IB_UPALL_1000M_X4_OFFSET    8
#define    RTL8367D_CFG_IB_UPALL_1000M_X4_MASK    0x100
#define    RTL8367D_CFG_IB_UP_1000M_X4_OFFSET    0
#define    RTL8367D_CFG_IB_UP_1000M_X4_MASK    0xFF

#define    RTL8367D_REG_PHY_STATUS    0x1e37
#define    RTL8367D_PHY_FATAL_OFFSET    10
#define    RTL8367D_PHY_FATAL_MASK    0x7C00
#define    RTL8367D_PHY_LANON_OFFSET    5
#define    RTL8367D_PHY_LANON_MASK    0x3E0
#define    RTL8367D_PHY_EXTINI_OFFSET    0
#define    RTL8367D_PHY_EXTINI_MASK    0x1F

#define    RTL8367D_REG_PHY_PCSXF    0x1e38
#define    RTL8367D_PHY_PCSXF_OFFSET    0
#define    RTL8367D_PHY_PCSXF_MASK    0x1F

#define    RTL8367D_REG_RDM_UPD_PERIOD    0x1e39
#define    RTL8367D_RSUPD_PERIOD_OFFSET    8
#define    RTL8367D_RSUPD_PERIOD_MASK    0xFF00
#define    RTL8367D_RRUPD_PERIOD_OFFSET    0
#define    RTL8367D_RRUPD_PERIOD_MASK    0xFF

#define    RTL8367D_REG_RDM_UPD_CTRL    0x1e3a
#define    RTL8367D_TMTENBIT_OFFSET    15
#define    RTL8367D_TMTENBIT_MASK    0x8000
#define    RTL8367D_TMLSB_OFFSET    12
#define    RTL8367D_TMLSB_MASK    0x7000
#define    RTL8367D_RR_SEL_MTHD_OFFSET    11
#define    RTL8367D_RR_SEL_MTHD_MASK    0x800
#define    RTL8367D_RRSTEP_OFFSET    6
#define    RTL8367D_RRSTEP_MASK    0x7C0
#define    RTL8367D_RRRND_SRC_SEL_OFFSET    5
#define    RTL8367D_RRRND_SRC_SEL_MASK    0x20
#define    RTL8367D_RRUPD_ONCE_OFFSET    4
#define    RTL8367D_RRUPD_ONCE_MASK    0x10
#define    RTL8367D_RRUPD_EN_OFFSET    3
#define    RTL8367D_RRUPD_EN_MASK    0x8
#define    RTL8367D_RSRND_SRC_SEL_OFFSET    2
#define    RTL8367D_RSRND_SRC_SEL_MASK    0x4
#define    RTL8367D_RSUPD_ONCE_OFFSET    1
#define    RTL8367D_RSUPD_ONCE_MASK    0x2
#define    RTL8367D_RSUPD_EN_OFFSET    0
#define    RTL8367D_RSUPD_EN_MASK    0x1

#define    RTL8367D_REG_RG_RDM_SEED_SRC    0x1e3b

#define    RTL8367D_REG_RG_RING_RATE    0x1e3c

#define    RTL8367D_REG_RING_RAGE_MASK_L    0x1e3d

#define    RTL8367D_REG_RING_RAGE_MASK_H    0x1e3e

#define    RTL8367D_REG_BIST_GMACRAM0    0x1e3f
#define    RTL8367D_GMACRAM_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_GMACRAM_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_GMACRAM_BIST_FAIL_OFFSET    14
#define    RTL8367D_GMACRAM_BIST_FAIL_MASK    0x4000
#define    RTL8367D_GMACRAM_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_GMACRAM_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_GMACRAM_BIST_DONE_OFFSET    12
#define    RTL8367D_GMACRAM_BIST_DONE_MASK    0x1000
#define    RTL8367D_GMACRAM_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_GMACRAM_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_GMACRAM_DYN_READ_EN_OFFSET    10
#define    RTL8367D_GMACRAM_DYN_READ_EN_MASK    0x400
#define    RTL8367D_GMACRAM_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_GMACRAM_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_GMACRAM_RME_OFFSET    8
#define    RTL8367D_GMACRAM_RME_MASK    0x100
#define    RTL8367D_GMACRAM_RM_OFFSET    4
#define    RTL8367D_GMACRAM_RM_MASK    0xF0
#define    RTL8367D_GMACRAM_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_GMACRAM_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_GMACRAM_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_GMACRAM_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_GMACRAM_BIST_MODE_OFFSET    1
#define    RTL8367D_GMACRAM_BIST_MODE_MASK    0x2
#define    RTL8367D_GMACRAM_BIST_RSTN_OFFSET    0
#define    RTL8367D_GMACRAM_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_GMACRAM1    0x1e40
#define    RTL8367D_BISD_CLK_SEL_OFFSET    12
#define    RTL8367D_BISD_CLK_SEL_MASK    0xF000
#define    RTL8367D_GMACRAM_LS_OFFSET    4
#define    RTL8367D_GMACRAM_LS_MASK    0x10
#define    RTL8367D_GMACRAM_TEST1_OFFSET    2
#define    RTL8367D_GMACRAM_TEST1_MASK    0xC
#define    RTL8367D_GMACRAM_DIAG_CLK_OFFSET    1
#define    RTL8367D_GMACRAM_DIAG_CLK_MASK    0x2
#define    RTL8367D_GMACRAM_DIAG_MODE_OFFSET    0
#define    RTL8367D_GMACRAM_DIAG_MODE_MASK    0x1

#define    RTL8367D_REG_BIST_GMACRAM2    0x1e41

#define    RTL8367D_REG_BIST_GMACRAM3    0x1e42

#define    RTL8367D_REG_BIST_GMACRAM4    0x1e43

#define    RTL8367D_REG_BIST_GMACRAM5    0x1e44

#define    RTL8367D_REG_BIST_GMACRAM6    0x1e45

#define    RTL8367D_REG_BIST_GMACRAM7    0x1e46
#define    RTL8367D_GMACRAM_MEB_OFFSET    13
#define    RTL8367D_GMACRAM_MEB_MASK    0x2000
#define    RTL8367D_GMACRAM_MEA_OFFSET    12
#define    RTL8367D_GMACRAM_MEA_MASK    0x1000
#define    RTL8367D_GMACRAM_ADRA_OFFSET    0
#define    RTL8367D_GMACRAM_ADRA_MASK    0x1FF

#define    RTL8367D_REG_BIST_GMACRAM8    0x1e47
#define    RTL8367D_BIST_GMACRAM8_OFFSET    0
#define    RTL8367D_BIST_GMACRAM8_MASK    0x1FF

#define    RTL8367D_REG_RDM_SEED_SRC    0x1e48
#define    RTL8367D_RDM_SEED_SRC_OFFSET    0
#define    RTL8367D_RDM_SEED_SRC_MASK    0x3FF

#define    RTL8367D_REG_RDM_FRC_SEED_SRC    0x1e49
#define    RTL8367D_RS_FRC_MODE_OFFSET    10
#define    RTL8367D_RS_FRC_MODE_MASK    0x400
#define    RTL8367D_VAL_SELECTED_RND_SRC_OFFSET    0
#define    RTL8367D_VAL_SELECTED_RND_SRC_MASK    0x3FF

#define    RTL8367D_REG_RDM_RING_SRC_1    0x1e4a
#define    RTL8367D_RDM_RING_SRC_1_OFFSET    0
#define    RTL8367D_RDM_RING_SRC_1_MASK    0x3FFF

#define    RTL8367D_REG_RDM_RING_SRC_0    0x1e4b

#define    RTL8367D_REG_RDM_FRC_RING_SRC_1    0x1e4c
#define    RTL8367D_RR_FRC_MODE_OFFSET    14
#define    RTL8367D_RR_FRC_MODE_MASK    0x4000
#define    RTL8367D_VAL_SELECTED_RING_SRC_29_16_OFFSET    0
#define    RTL8367D_VAL_SELECTED_RING_SRC_29_16_MASK    0x3FFF

#define    RTL8367D_REG_RDM_FRC_RING_SRC_0    0x1e4d

/* (16'h1f00)patch_reg */

#define    RTL8367D_REG_INDRECT_ACCESS_CTRL    0x1f00
#define    RTL8367D_RW_OFFSET    1
#define    RTL8367D_RW_MASK    0x2
#define    RTL8367D_CMD_OFFSET    0
#define    RTL8367D_CMD_MASK    0x1

#define    RTL8367D_REG_INDRECT_ACCESS_STATUS    0x1f01
#define    RTL8367D_INDRECT_ACCESS_STATUS_OFFSET    2
#define    RTL8367D_INDRECT_ACCESS_STATUS_MASK    0x4

#define    RTL8367D_REG_INDRECT_ACCESS_ADDRESS    0x1f02

#define    RTL8367D_REG_INDRECT_ACCESS_WRITE_DATA    0x1f03

#define    RTL8367D_REG_INDRECT_ACCESS_READ_DATA    0x1f04

/* (16'h6100)nctl_reg */

#define    RTL8367D_REG_NCTL_0    0x6100
#define    RTL8367D_NCTL_CPU_EN_OFFSET    12
#define    RTL8367D_NCTL_CPU_EN_MASK    0x3000
#define    RTL8367D_NCTL_PATCH_MODE_EN_OFFSET    11
#define    RTL8367D_NCTL_PATCH_MODE_EN_MASK    0x800
#define    RTL8367D_NCTL_PC_SPECIFY_EN_OFFSET    10
#define    RTL8367D_NCTL_PC_SPECIFY_EN_MASK    0x400
#define    RTL8367D_NCTL_PC_SPECIFY_OFFSET    0
#define    RTL8367D_NCTL_PC_SPECIFY_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P00_0    0x6101
#define    RTL8367D_NCTL_BP_EN_P00_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P00_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P00_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P00_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P00_1    0x6102
#define    RTL8367D_NCTL_P00_1_OFFSET    0
#define    RTL8367D_NCTL_P00_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P01_0    0x6103
#define    RTL8367D_NCTL_BP_EN_P01_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P01_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P01_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P01_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P01_1    0x6104
#define    RTL8367D_NCTL_P01_1_OFFSET    0
#define    RTL8367D_NCTL_P01_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P02_0    0x6105
#define    RTL8367D_NCTL_BP_EN_P02_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P02_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P02_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P02_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P02_1    0x6106
#define    RTL8367D_NCTL_P02_1_OFFSET    0
#define    RTL8367D_NCTL_P02_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P03_0    0x6107
#define    RTL8367D_NCTL_BP_EN_P03_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P03_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P03_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P03_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P03_1    0x6108
#define    RTL8367D_NCTL_P03_1_OFFSET    0
#define    RTL8367D_NCTL_P03_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P04_0    0x6109
#define    RTL8367D_NCTL_BP_EN_P04_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P04_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P04_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P04_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P04_1    0x610a
#define    RTL8367D_NCTL_P04_1_OFFSET    0
#define    RTL8367D_NCTL_P04_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P05_0    0x610b
#define    RTL8367D_NCTL_BP_EN_P05_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P05_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P05_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P05_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P05_1    0x610c
#define    RTL8367D_NCTL_P05_1_OFFSET    0
#define    RTL8367D_NCTL_P05_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P06_0    0x610d
#define    RTL8367D_NCTL_BP_EN_P06_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P06_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P06_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P06_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P06_1    0x610e
#define    RTL8367D_NCTL_P06_1_OFFSET    0
#define    RTL8367D_NCTL_P06_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P07_0    0x610f
#define    RTL8367D_NCTL_BP_EN_P07_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P07_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P07_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P07_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P07_1    0x6110
#define    RTL8367D_NCTL_P07_1_OFFSET    0
#define    RTL8367D_NCTL_P07_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P08_0    0x6111
#define    RTL8367D_NCTL_BP_EN_P08_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P08_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P08_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P08_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P08_1    0x6112
#define    RTL8367D_NCTL_P08_1_OFFSET    0
#define    RTL8367D_NCTL_P08_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P09_0    0x6113
#define    RTL8367D_NCTL_BP_EN_P09_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P09_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P09_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P09_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P09_1    0x6114
#define    RTL8367D_NCTL_P09_1_OFFSET    0
#define    RTL8367D_NCTL_P09_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P10_0    0x6115
#define    RTL8367D_NCTL_BP_EN_P10_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P10_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P10_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P10_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P10_1    0x6116
#define    RTL8367D_NCTL_P10_1_OFFSET    0
#define    RTL8367D_NCTL_P10_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P11_0    0x6117
#define    RTL8367D_NCTL_BP_EN_P11_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P11_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P11_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P11_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P11_1    0x6118
#define    RTL8367D_NCTL_P11_1_OFFSET    0
#define    RTL8367D_NCTL_P11_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P12_0    0x6119
#define    RTL8367D_NCTL_BP_EN_P12_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P12_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P12_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P12_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P12_1    0x611a
#define    RTL8367D_NCTL_P12_1_OFFSET    0
#define    RTL8367D_NCTL_P12_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P13_0    0x611b
#define    RTL8367D_NCTL_BP_EN_P13_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P13_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P13_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P13_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P13_1    0x611c
#define    RTL8367D_NCTL_P13_1_OFFSET    0
#define    RTL8367D_NCTL_P13_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P14_0    0x611d
#define    RTL8367D_NCTL_BP_EN_P14_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P14_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P14_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P14_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P14_1    0x611e
#define    RTL8367D_NCTL_P14_1_OFFSET    0
#define    RTL8367D_NCTL_P14_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P15_0    0x611f
#define    RTL8367D_NCTL_BP_EN_P15_OFFSET    10
#define    RTL8367D_NCTL_BP_EN_P15_MASK    0x400
#define    RTL8367D_NCTL_BP_ADDR_P15_OFFSET    0
#define    RTL8367D_NCTL_BP_ADDR_P15_MASK    0x3FF

#define    RTL8367D_REG_NCTL_P15_1    0x6120
#define    RTL8367D_NCTL_P15_1_OFFSET    0
#define    RTL8367D_NCTL_P15_1_MASK    0x3FF

#define    RTL8367D_REG_NCTL_SRCA_VAL0    0x6121

#define    RTL8367D_REG_NCTL_SRCA_VAL1    0x6122

#define    RTL8367D_REG_NCTL_SRCA_VAL2    0x6123

#define    RTL8367D_REG_NCTL_SRCB_VAL0    0x6124

#define    RTL8367D_REG_NCTL_SRCB_VAL1    0x6125

#define    RTL8367D_REG_NCTL_SRCB_VAL2    0x6126

#define    RTL8367D_REG_NCTL_CIO_SEL    0x6127
#define    RTL8367D_NCTL_CI_SEL_OFFSET    8
#define    RTL8367D_NCTL_CI_SEL_MASK    0xFF00
#define    RTL8367D_NCTL_CO_SEL_OFFSET    0
#define    RTL8367D_NCTL_CO_SEL_MASK    0xFF

#define    RTL8367D_REG_NCTL_CO_MON    0x6128

#define    RTL8367D_REG_NCTL_CI_MSB_MON    0x6129

#define    RTL8367D_REG_NCTL_PC_MON    0x612a
#define    RTL8367D_NCTL_PC_MON_OFFSET    0
#define    RTL8367D_NCTL_PC_MON_MASK    0x3FF

#define    RTL8367D_REG_NCTL_SRAM_IN    0x612b

#define    RTL8367D_REG_NCTL_EN    0x612f
#define    RTL8367D_NCTL_RSTB_BITERR_EN_OFFSET    3
#define    RTL8367D_NCTL_RSTB_BITERR_EN_MASK    0x8
#define    RTL8367D_NCTL_EN_OFFSET    2
#define    RTL8367D_NCTL_EN_MASK    0x4
#define    RTL8367D_RG_NCTL_SEL_OFFSET    0
#define    RTL8367D_RG_NCTL_SEL_MASK    0x3

#define    RTL8367D_REG_NCTL_CI_LSB_MON    0x6134

#define    RTL8367D_REG_NCTL_RAM_INDACS_0    0x6135
#define    RTL8367D_NCTL_CMD_OFFSET    14
#define    RTL8367D_NCTL_CMD_MASK    0x4000
#define    RTL8367D_NCTL_WR_OFFSET    13
#define    RTL8367D_NCTL_WR_MASK    0x2000
#define    RTL8367D_NCTL_CMD_TMOUT_OFFSET    10
#define    RTL8367D_NCTL_CMD_TMOUT_MASK    0x1C00
#define    RTL8367D_NCTL_ADR_OFFSET    0
#define    RTL8367D_NCTL_ADR_MASK    0x3FF

#define    RTL8367D_REG_NCTL_RAM_INDACS_1    0x6136

#define    RTL8367D_REG_NCTL_RAM_INDACS_2    0x6137

/* (16'h6200)fib_page */

#define    RTL8367D_REG_FIB_CFG00    0x6200
#define    RTL8367D_CFG_FIB_RST_OFFSET    15
#define    RTL8367D_CFG_FIB_RST_MASK    0x8000
#define    RTL8367D_CFG_FIB_LPK_OFFSET    14
#define    RTL8367D_CFG_FIB_LPK_MASK    0x4000
#define    RTL8367D_CFG_FIB_SPD_RD_0_OFFSET    13
#define    RTL8367D_CFG_FIB_SPD_RD_0_MASK    0x2000
#define    RTL8367D_CFG_FIB_ANEN_OFFSET    12
#define    RTL8367D_CFG_FIB_ANEN_MASK    0x1000
#define    RTL8367D_CFG_FIB_PDOWN_OFFSET    11
#define    RTL8367D_CFG_FIB_PDOWN_MASK    0x800
#define    RTL8367D_CFG_FIB_ISO_OFFSET    10
#define    RTL8367D_CFG_FIB_ISO_MASK    0x400
#define    RTL8367D_CFG_FIB_RESTART_OFFSET    9
#define    RTL8367D_CFG_FIB_RESTART_MASK    0x200
#define    RTL8367D_CFG_FIB_FULLDUP_OFFSET    8
#define    RTL8367D_CFG_FIB_FULLDUP_MASK    0x100
#define    RTL8367D_CFG_FIB_SPD_RD_1_OFFSET    6
#define    RTL8367D_CFG_FIB_SPD_RD_1_MASK    0x40
#define    RTL8367D_CFG_FIB_FRCTX_OFFSET    5
#define    RTL8367D_CFG_FIB_FRCTX_MASK    0x20

#define    RTL8367D_REG_FIB_CFG01    0x6201
#define    RTL8367D_CAPBILITY_OFFSET    6
#define    RTL8367D_CAPBILITY_MASK    0xFFC0
#define    RTL8367D_AN_COMPLETE_OFFSET    5
#define    RTL8367D_AN_COMPLETE_MASK    0x20
#define    RTL8367D_R_FAULT_OFFSET    4
#define    RTL8367D_R_FAULT_MASK    0x10
#define    RTL8367D_NWAY_ABILITY_OFFSET    3
#define    RTL8367D_NWAY_ABILITY_MASK    0x8
#define    RTL8367D_LINK_STATUS_OFFSET    2
#define    RTL8367D_LINK_STATUS_MASK    0x4
#define    RTL8367D_JABBER_DETECT_OFFSET    1
#define    RTL8367D_JABBER_DETECT_MASK    0x2
#define    RTL8367D_EXTENDED_CAPBILITY_OFFSET    0
#define    RTL8367D_EXTENDED_CAPBILITY_MASK    0x1

#define    RTL8367D_REG_FIB_CFG02    0x6202

#define    RTL8367D_REG_FIB_CFG03    0x6203
#define    RTL8367D_REALTEK_OUI5_0_OFFSET    10
#define    RTL8367D_REALTEK_OUI5_0_MASK    0xFC00
#define    RTL8367D_MODEL_NO_OFFSET    4
#define    RTL8367D_MODEL_NO_MASK    0x3F0
#define    RTL8367D_REVISION_NO_OFFSET    0
#define    RTL8367D_REVISION_NO_MASK    0xF

#define    RTL8367D_REG_FIB_CFG04    0x6204

#define    RTL8367D_REG_FIB_CFG05    0x6205

#define    RTL8367D_REG_FIB_CFG06    0x6206
#define    RTL8367D_FIB_NP_EN_OFFSET    2
#define    RTL8367D_FIB_NP_EN_MASK    0x4
#define    RTL8367D_RXPAGE_OFFSET    1
#define    RTL8367D_RXPAGE_MASK    0x2

#define    RTL8367D_REG_FIB_CFG07    0x6207

#define    RTL8367D_REG_FIB_CFG08    0x6208

#define    RTL8367D_REG_FIB_CFG09    0x6209

#define    RTL8367D_REG_FIB_CFG10    0x620a

#define    RTL8367D_REG_FIB_CFG11    0x620b

#define    RTL8367D_REG_FIB_CFG12    0x620c

#define    RTL8367D_REG_FIB_CFG13    0x620d
#define    RTL8367D_INDR_FUNC_OFFSET    14
#define    RTL8367D_INDR_FUNC_MASK    0xC000
#define    RTL8367D_FIB_CFG13_DUMMY_OFFSET    5
#define    RTL8367D_FIB_CFG13_DUMMY_MASK    0x3FE0
#define    RTL8367D_INDR_DEVAD_OFFSET    0
#define    RTL8367D_INDR_DEVAD_MASK    0x1F

#define    RTL8367D_REG_FIB_CFG14    0x620e

#define    RTL8367D_REG_FIB_CFG15    0x620f

/* (16'h6500)SWR_reg */

#define    RTL8367D_REG_SWR_REG0    0x6500

#define    RTL8367D_REG_SWR_REG1    0x6501

#define    RTL8367D_REG_SWR_REG2    0x6502

#define    RTL8367D_REG_SWR_REG3    0x6503

#define    RTL8367D_REG_SWR_REG4    0x6504

#define    RTL8367D_REG_SWR_REG5    0x6505

/* (16'h6600)sds_indacs_reg */

#define    RTL8367D_REG_SDS_INDACS_CMD    0x6600
#define    RTL8367D_SDS_CMD_BUSY_OFFSET    8
#define    RTL8367D_SDS_CMD_BUSY_MASK    0x100
#define    RTL8367D_SDS_CMD_OFFSET    7
#define    RTL8367D_SDS_CMD_MASK    0x80
#define    RTL8367D_SDS_RWOP_OFFSET    6
#define    RTL8367D_SDS_RWOP_MASK    0x40
#define    RTL8367D_SDS_INDEX_OFFSET    0
#define    RTL8367D_SDS_INDEX_MASK    0x3F

#define    RTL8367D_REG_SDS_INDACS_ADR    0x6601
#define    RTL8367D_SDS_PAGE_OFFSET    5
#define    RTL8367D_SDS_PAGE_MASK    0x7E0
#define    RTL8367D_SDS_REGAD_OFFSET    0
#define    RTL8367D_SDS_REGAD_MASK    0x1F

#define    RTL8367D_REG_SDS_INDACS_DATA    0x6602

/* (16'h6700)bist_reg */

#define    RTL8367D_REG_BIST_TCAM    0x6700
#define    RTL8367D_TCAM_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_TCAM_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_TCAM_BIST_FAIL_OFFSET    14
#define    RTL8367D_TCAM_BIST_FAIL_MASK    0x4000
#define    RTL8367D_TCAM_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_TCAM_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_TCAM_BIST_DONE_OFFSET    12
#define    RTL8367D_TCAM_BIST_DONE_MASK    0x1000
#define    RTL8367D_TCAM_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_TCAM_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_TCAM_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_TCAM_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_TCAM_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_TCAM_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_TCAM_BIST_MODE_OFFSET    1
#define    RTL8367D_TCAM_BIST_MODE_MASK    0x2
#define    RTL8367D_TCAM_BIST_RSTN_OFFSET    0
#define    RTL8367D_TCAM_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_L2    0x6701
#define    RTL8367D_L2_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_L2_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_L2_BIST_FAIL_OFFSET    14
#define    RTL8367D_L2_BIST_FAIL_MASK    0x4000
#define    RTL8367D_L2_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_L2_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_L2_BIST_DONE_OFFSET    12
#define    RTL8367D_L2_BIST_DONE_MASK    0x1000
#define    RTL8367D_L2_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_L2_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_L2_DYN_READ_EN_OFFSET    10
#define    RTL8367D_L2_DYN_READ_EN_MASK    0x400
#define    RTL8367D_L2_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_L2_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_L2_RME_OFFSET    8
#define    RTL8367D_L2_RME_MASK    0x100
#define    RTL8367D_L2_RM_OFFSET    4
#define    RTL8367D_L2_RM_MASK    0xF0
#define    RTL8367D_L2_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_L2_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_L2_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_L2_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_L2_BIST_MODE_OFFSET    1
#define    RTL8367D_L2_BIST_MODE_MASK    0x2
#define    RTL8367D_L2_BIST_RSTN_OFFSET    0
#define    RTL8367D_L2_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_OUTQ    0x6702
#define    RTL8367D_OUTQ_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_OUTQ_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_OUTQ_BIST_FAIL_OFFSET    14
#define    RTL8367D_OUTQ_BIST_FAIL_MASK    0x4000
#define    RTL8367D_OUTQ_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_OUTQ_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_OUTQ_BIST_DONE_OFFSET    12
#define    RTL8367D_OUTQ_BIST_DONE_MASK    0x1000
#define    RTL8367D_OUTQ_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_OUTQ_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_OUTQ_DYN_READ_EN_OFFSET    10
#define    RTL8367D_OUTQ_DYN_READ_EN_MASK    0x400
#define    RTL8367D_OUTQ_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_OUTQ_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_OUTQ_RME_OFFSET    8
#define    RTL8367D_OUTQ_RME_MASK    0x100
#define    RTL8367D_OUTQ_RM_OFFSET    4
#define    RTL8367D_OUTQ_RM_MASK    0xF0
#define    RTL8367D_OUTQ_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_OUTQ_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_OUTQ_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_OUTQ_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_OUTQ_BIST_MODE_OFFSET    1
#define    RTL8367D_OUTQ_BIST_MODE_MASK    0x2
#define    RTL8367D_OUTQ_BIST_RSTN_OFFSET    0
#define    RTL8367D_OUTQ_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_PB    0x6703
#define    RTL8367D_PB_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_PB_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_PB_BIST_FAIL_OFFSET    14
#define    RTL8367D_PB_BIST_FAIL_MASK    0x4000
#define    RTL8367D_PB_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_PB_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_PB_BIST_DONE_OFFSET    12
#define    RTL8367D_PB_BIST_DONE_MASK    0x1000
#define    RTL8367D_PB_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_PB_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_PB_DYN_READ_EN_OFFSET    10
#define    RTL8367D_PB_DYN_READ_EN_MASK    0x400
#define    RTL8367D_PB_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_PB_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_PB_RME_OFFSET    8
#define    RTL8367D_PB_RME_MASK    0x100
#define    RTL8367D_PB_RM_OFFSET    4
#define    RTL8367D_PB_RM_MASK    0xF0
#define    RTL8367D_PB_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_PB_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_PB_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_PB_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_PB_BIST_MODE_OFFSET    1
#define    RTL8367D_PB_BIST_MODE_MASK    0x2
#define    RTL8367D_PB_BIST_RSTN_OFFSET    0
#define    RTL8367D_PB_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_ACT    0x6704
#define    RTL8367D_ACT_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_ACT_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_ACT_BIST_FAIL_OFFSET    14
#define    RTL8367D_ACT_BIST_FAIL_MASK    0x4000
#define    RTL8367D_ACT_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_ACT_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_ACT_BIST_DONE_OFFSET    12
#define    RTL8367D_ACT_BIST_DONE_MASK    0x1000
#define    RTL8367D_ACT_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_ACT_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_ACT_DYN_READ_EN_OFFSET    10
#define    RTL8367D_ACT_DYN_READ_EN_MASK    0x400
#define    RTL8367D_ACT_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_ACT_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_ACT_RME_OFFSET    8
#define    RTL8367D_ACT_RME_MASK    0x100
#define    RTL8367D_ACT_RM_OFFSET    4
#define    RTL8367D_ACT_RM_MASK    0xF0
#define    RTL8367D_ACT_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_ACT_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_ACT_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_ACT_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_ACT_BIST_MODE_OFFSET    1
#define    RTL8367D_ACT_BIST_MODE_MASK    0x2
#define    RTL8367D_ACT_BIST_RSTN_OFFSET    0
#define    RTL8367D_ACT_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_HT    0x6705
#define    RTL8367D_HT_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_HT_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_HT_BIST_FAIL_OFFSET    14
#define    RTL8367D_HT_BIST_FAIL_MASK    0x4000
#define    RTL8367D_HT_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_HT_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_HT_BIST_DONE_OFFSET    12
#define    RTL8367D_HT_BIST_DONE_MASK    0x1000
#define    RTL8367D_HT_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_HT_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_HT_DYN_READ_EN_OFFSET    10
#define    RTL8367D_HT_DYN_READ_EN_MASK    0x400
#define    RTL8367D_HT_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_HT_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_HT_RME_OFFSET    8
#define    RTL8367D_HT_RME_MASK    0x100
#define    RTL8367D_HT_RM_OFFSET    4
#define    RTL8367D_HT_RM_MASK    0xF0
#define    RTL8367D_HT_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_HT_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_HT_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_HT_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_HT_BIST_MODE_OFFSET    1
#define    RTL8367D_HT_BIST_MODE_MASK    0x2
#define    RTL8367D_HT_BIST_RSTN_OFFSET    0
#define    RTL8367D_HT_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_MIB    0x6706
#define    RTL8367D_MIB_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_MIB_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_MIB_BIST_FAIL_OFFSET    14
#define    RTL8367D_MIB_BIST_FAIL_MASK    0x4000
#define    RTL8367D_MIB_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_MIB_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_MIB_BIST_DONE_OFFSET    12
#define    RTL8367D_MIB_BIST_DONE_MASK    0x1000
#define    RTL8367D_MIB_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_MIB_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_MIB_DYN_READ_EN_OFFSET    10
#define    RTL8367D_MIB_DYN_READ_EN_MASK    0x400
#define    RTL8367D_MIB_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_MIB_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_MIB_RME_OFFSET    8
#define    RTL8367D_MIB_RME_MASK    0x100
#define    RTL8367D_MIB_RM_OFFSET    4
#define    RTL8367D_MIB_RM_MASK    0xF0
#define    RTL8367D_MIB_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_MIB_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_MIB_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_MIB_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_MIB_BIST_MODE_OFFSET    1
#define    RTL8367D_MIB_BIST_MODE_MASK    0x2
#define    RTL8367D_MIB_BIST_RSTN_OFFSET    0
#define    RTL8367D_MIB_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_CVLAN    0x6707
#define    RTL8367D_CVLAN_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_CVLAN_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_CVLAN_BIST_FAIL_OFFSET    14
#define    RTL8367D_CVLAN_BIST_FAIL_MASK    0x4000
#define    RTL8367D_CVLAN_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_CVLAN_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_CVLAN_BIST_DONE_OFFSET    12
#define    RTL8367D_CVLAN_BIST_DONE_MASK    0x1000
#define    RTL8367D_CVLAN_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_CVLAN_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_CVLAN_DYN_READ_EN_OFFSET    10
#define    RTL8367D_CVLAN_DYN_READ_EN_MASK    0x400
#define    RTL8367D_CVLAN_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_CVLAN_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_CVLAN_RME_OFFSET    8
#define    RTL8367D_CVLAN_RME_MASK    0x100
#define    RTL8367D_CVLAN_RM_OFFSET    4
#define    RTL8367D_CVLAN_RM_MASK    0xF0
#define    RTL8367D_CVLAN_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_CVLAN_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_CVLAN_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_CVLAN_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_CVLAN_BIST_MODE_OFFSET    1
#define    RTL8367D_CVLAN_BIST_MODE_MASK    0x2
#define    RTL8367D_CVLAN_BIST_RSTN_OFFSET    0
#define    RTL8367D_CVLAN_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_HSACTRL    0x6708
#define    RTL8367D_HSACTRL_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_HSACTRL_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_HSACTRL_BIST_FAIL_OFFSET    14
#define    RTL8367D_HSACTRL_BIST_FAIL_MASK    0x4000
#define    RTL8367D_HSACTRL_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_HSACTRL_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_HSACTRL_BIST_DONE_OFFSET    12
#define    RTL8367D_HSACTRL_BIST_DONE_MASK    0x1000
#define    RTL8367D_HSACTRL_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_HSACTRL_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_HSACTRL_DYN_READ_EN_OFFSET    10
#define    RTL8367D_HSACTRL_DYN_READ_EN_MASK    0x400
#define    RTL8367D_HSACTRL_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_HSACTRL_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_HSACTRL_RME_OFFSET    8
#define    RTL8367D_HSACTRL_RME_MASK    0x100
#define    RTL8367D_HSACTRL_RM_OFFSET    4
#define    RTL8367D_HSACTRL_RM_MASK    0xF0
#define    RTL8367D_HSACTRL_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_HSACTRL_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_HSACTRL_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_HSACTRL_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_HSACTRL_BIST_MODE_OFFSET    1
#define    RTL8367D_HSACTRL_BIST_MODE_MASK    0x2
#define    RTL8367D_HSACTRL_BIST_RSTN_OFFSET    0
#define    RTL8367D_HSACTRL_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_ERAM    0x6709
#define    RTL8367D_ERAM_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_ERAM_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_ERAM_BIST_FAIL_OFFSET    14
#define    RTL8367D_ERAM_BIST_FAIL_MASK    0x4000
#define    RTL8367D_ERAM_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_ERAM_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_ERAM_BIST_DONE_OFFSET    12
#define    RTL8367D_ERAM_BIST_DONE_MASK    0x1000
#define    RTL8367D_ERAM_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_ERAM_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_ERAM_DYN_READ_EN_OFFSET    10
#define    RTL8367D_ERAM_DYN_READ_EN_MASK    0x400
#define    RTL8367D_ERAM_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_ERAM_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_ERAM_RME_OFFSET    8
#define    RTL8367D_ERAM_RME_MASK    0x100
#define    RTL8367D_ERAM_RM_OFFSET    4
#define    RTL8367D_ERAM_RM_MASK    0xF0
#define    RTL8367D_ERAM_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_ERAM_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_ERAM_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_ERAM_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_ERAM_BIST_MODE_OFFSET    1
#define    RTL8367D_ERAM_BIST_MODE_MASK    0x2
#define    RTL8367D_ERAM_BIST_RSTN_OFFSET    0
#define    RTL8367D_ERAM_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_IRAM    0x670a
#define    RTL8367D_IRAM_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_IRAM_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_IRAM_BIST_FAIL_OFFSET    14
#define    RTL8367D_IRAM_BIST_FAIL_MASK    0x4000
#define    RTL8367D_IRAM_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_IRAM_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_IRAM_BIST_DONE_OFFSET    12
#define    RTL8367D_IRAM_BIST_DONE_MASK    0x1000
#define    RTL8367D_IRAM_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_IRAM_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_IRAM_DYN_READ_EN_OFFSET    10
#define    RTL8367D_IRAM_DYN_READ_EN_MASK    0x400
#define    RTL8367D_IRAM_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_IRAM_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_IRAM_RME_OFFSET    8
#define    RTL8367D_IRAM_RME_MASK    0x100
#define    RTL8367D_IRAM_RM_OFFSET    4
#define    RTL8367D_IRAM_RM_MASK    0xF0
#define    RTL8367D_IRAM_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_IRAM_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_IRAM_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_IRAM_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_IRAM_BIST_MODE_OFFSET    1
#define    RTL8367D_IRAM_BIST_MODE_MASK    0x2
#define    RTL8367D_IRAM_BIST_RSTN_OFFSET    0
#define    RTL8367D_IRAM_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_IROM    0x670b
#define    RTL8367D_IROM_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_IROM_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_IROM_BIST_FAIL_OFFSET    14
#define    RTL8367D_IROM_BIST_FAIL_MASK    0x4000
#define    RTL8367D_IROM_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_IROM_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_IROM_BIST_DONE_OFFSET    12
#define    RTL8367D_IROM_BIST_DONE_MASK    0x1000
#define    RTL8367D_IROM_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_IROM_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_IROM_DYN_READ_EN_OFFSET    10
#define    RTL8367D_IROM_DYN_READ_EN_MASK    0x400
#define    RTL8367D_IROM_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_IROM_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_IROM_RME_OFFSET    8
#define    RTL8367D_IROM_RME_MASK    0x100
#define    RTL8367D_IROM_RM_OFFSET    4
#define    RTL8367D_IROM_RM_MASK    0xF0
#define    RTL8367D_IROM_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_IROM_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_IROM_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_IROM_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_IROM_BIST_MODE_OFFSET    1
#define    RTL8367D_IROM_BIST_MODE_MASK    0x2
#define    RTL8367D_IROM_BIST_RSTN_OFFSET    0
#define    RTL8367D_IROM_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_NCTLRAM    0x670c
#define    RTL8367D_NCTLRAM_DRF_BIST_FAIL_OFFSET    15
#define    RTL8367D_NCTLRAM_DRF_BIST_FAIL_MASK    0x8000
#define    RTL8367D_NCTLRAM_BIST_FAIL_OFFSET    14
#define    RTL8367D_NCTLRAM_BIST_FAIL_MASK    0x4000
#define    RTL8367D_NCTLRAM_DRF_BIST_DONE_OFFSET    13
#define    RTL8367D_NCTLRAM_DRF_BIST_DONE_MASK    0x2000
#define    RTL8367D_NCTLRAM_BIST_DONE_OFFSET    12
#define    RTL8367D_NCTLRAM_BIST_DONE_MASK    0x1000
#define    RTL8367D_NCTLRAM_DRF_START_PAUSE_OFFSET    11
#define    RTL8367D_NCTLRAM_DRF_START_PAUSE_MASK    0x800
#define    RTL8367D_NCTLRAM_DYN_READ_EN_OFFSET    10
#define    RTL8367D_NCTLRAM_DYN_READ_EN_MASK    0x400
#define    RTL8367D_NCTLRAM_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_NCTLRAM_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_NCTLRAM_RME_OFFSET    8
#define    RTL8367D_NCTLRAM_RME_MASK    0x100
#define    RTL8367D_NCTLRAM_RM_OFFSET    4
#define    RTL8367D_NCTLRAM_RM_MASK    0xF0
#define    RTL8367D_NCTLRAM_DRF_TEST_RESUME_OFFSET    3
#define    RTL8367D_NCTLRAM_DRF_TEST_RESUME_MASK    0x8
#define    RTL8367D_NCTLRAM_DRF_BIST_MODE_OFFSET    2
#define    RTL8367D_NCTLRAM_DRF_BIST_MODE_MASK    0x4
#define    RTL8367D_NCTLRAM_BIST_MODE_OFFSET    1
#define    RTL8367D_NCTLRAM_BIST_MODE_MASK    0x2
#define    RTL8367D_NCTLRAM_BIST_RSTN_OFFSET    0
#define    RTL8367D_NCTLRAM_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_BIST_NCTLROM    0x670d
#define    RTL8367D_NCTLROM_BIST_FAIL_OFFSET    14
#define    RTL8367D_NCTLROM_BIST_FAIL_MASK    0x4000
#define    RTL8367D_NCTLROM_BIST_DONE_OFFSET    12
#define    RTL8367D_NCTLROM_BIST_DONE_MASK    0x1000
#define    RTL8367D_NCTLROM_BIST_LOOP_MODE_OFFSET    9
#define    RTL8367D_NCTLROM_BIST_LOOP_MODE_MASK    0x200
#define    RTL8367D_NCTLROM_RME_OFFSET    8
#define    RTL8367D_NCTLROM_RME_MASK    0x100
#define    RTL8367D_NCTLROM_RM_OFFSET    4
#define    RTL8367D_NCTLROM_RM_MASK    0xF0
#define    RTL8367D_NCTLROM_BIST_MODE_OFFSET    1
#define    RTL8367D_NCTLROM_BIST_MODE_MASK    0x2
#define    RTL8367D_NCTLROM_BIST_RSTN_OFFSET    0
#define    RTL8367D_NCTLROM_BIST_RSTN_MASK    0x1

#define    RTL8367D_REG_SET_MISR_LSB    0x6710

#define    RTL8367D_REG_SET_MISR_MSB    0x6711

#define    RTL8367D_REG_GET_MISR_LSB    0x6712

#define    RTL8367D_REG_GET_MISR_MSB    0x6713

#define    RTL8367D_REG_BIST_GRP_L2    0x6714
#define    RTL8367D_BIST_GRP_L2_OFFSET    0
#define    RTL8367D_BIST_GRP_L2_MASK    0xF

#define    RTL8367D_REG_BIST_GRP_OUTQ    0x6715
#define    RTL8367D_BIST_GRP_OUTQ_OFFSET    0
#define    RTL8367D_BIST_GRP_OUTQ_MASK    0x7F

#define    RTL8367D_REG_BIST_GRP_PB    0x6716
#define    RTL8367D_BIST_GRP_PB_OFFSET    0
#define    RTL8367D_BIST_GRP_PB_MASK    0xFF

#define    RTL8367D_REG_BIST_FAIL_L2    0x6717
#define    RTL8367D_BIST_FAIL_L2_OFFSET    0
#define    RTL8367D_BIST_FAIL_L2_MASK    0xF

#define    RTL8367D_REG_BIST_FAIL_OUTQ    0x6718
#define    RTL8367D_BIST_FAIL_OUTQ_OFFSET    0
#define    RTL8367D_BIST_FAIL_OUTQ_MASK    0x7F

#define    RTL8367D_REG_BIST_FAIL_PB    0x6719
#define    RTL8367D_BIST_FAIL_PB_OFFSET    0
#define    RTL8367D_BIST_FAIL_PB_MASK    0xFF

#define    RTL8367D_REG_BIST_DRF_FAIL_L2    0x671a
#define    RTL8367D_BIST_DRF_FAIL_L2_OFFSET    0
#define    RTL8367D_BIST_DRF_FAIL_L2_MASK    0xF

#define    RTL8367D_REG_BIST_DRF_FAIL_OUTQ    0x671b
#define    RTL8367D_BIST_DRF_FAIL_OUTQ_OFFSET    0
#define    RTL8367D_BIST_DRF_FAIL_OUTQ_MASK    0x7F

#define    RTL8367D_REG_BIST_DRF_FAIL_PB    0x671c
#define    RTL8367D_BIST_DRF_FAIL_PB_OFFSET    0
#define    RTL8367D_BIST_DRF_FAIL_PB_MASK    0xFF

#define    RTL8367D_REG_BIST_CFG_LS    0x671d
#define    RTL8367D_NCTLROM_LS_OFFSET    13
#define    RTL8367D_NCTLROM_LS_MASK    0x2000
#define    RTL8367D_NCTLRAM_LS_OFFSET    12
#define    RTL8367D_NCTLRAM_LS_MASK    0x1000
#define    RTL8367D_IROM_LS_OFFSET    11
#define    RTL8367D_IROM_LS_MASK    0x800
#define    RTL8367D_IRAM_LS_OFFSET    10
#define    RTL8367D_IRAM_LS_MASK    0x400
#define    RTL8367D_ERAM_LS_OFFSET    9
#define    RTL8367D_ERAM_LS_MASK    0x200
#define    RTL8367D_HSACTRL_LS_OFFSET    8
#define    RTL8367D_HSACTRL_LS_MASK    0x100
#define    RTL8367D_CVLAN_LS_OFFSET    7
#define    RTL8367D_CVLAN_LS_MASK    0x80
#define    RTL8367D_MIB_LS_OFFSET    6
#define    RTL8367D_MIB_LS_MASK    0x40
#define    RTL8367D_HT_LS_OFFSET    5
#define    RTL8367D_HT_LS_MASK    0x20
#define    RTL8367D_ACT_LS_OFFSET    4
#define    RTL8367D_ACT_LS_MASK    0x10
#define    RTL8367D_PB_LS_OFFSET    3
#define    RTL8367D_PB_LS_MASK    0x8
#define    RTL8367D_OUTQ_LS_OFFSET    2
#define    RTL8367D_OUTQ_LS_MASK    0x4
#define    RTL8367D_L2_LS_OFFSET    1
#define    RTL8367D_L2_LS_MASK    0x2

#define    RTL8367D_REG_BIST_CFG_TEST1    0x671e
#define    RTL8367D_HT_TESTRWM_OFFSET    14
#define    RTL8367D_HT_TESTRWM_MASK    0x4000
#define    RTL8367D_NCTLROM_TEST1_OFFSET    13
#define    RTL8367D_NCTLROM_TEST1_MASK    0x2000
#define    RTL8367D_NCTLRAM_TEST1_OFFSET    12
#define    RTL8367D_NCTLRAM_TEST1_MASK    0x1000
#define    RTL8367D_IROM_TEST1_OFFSET    11
#define    RTL8367D_IROM_TEST1_MASK    0x800
#define    RTL8367D_IRAM_TEST1_OFFSET    10
#define    RTL8367D_IRAM_TEST1_MASK    0x400
#define    RTL8367D_ERAM_TEST1_OFFSET    9
#define    RTL8367D_ERAM_TEST1_MASK    0x200
#define    RTL8367D_HSACTRL_TEST1_OFFSET    8
#define    RTL8367D_HSACTRL_TEST1_MASK    0x100
#define    RTL8367D_CVLAN_TEST1_OFFSET    7
#define    RTL8367D_CVLAN_TEST1_MASK    0x80
#define    RTL8367D_MIB_TEST1_OFFSET    6
#define    RTL8367D_MIB_TEST1_MASK    0x40
#define    RTL8367D_HT_TEST1_OFFSET    5
#define    RTL8367D_HT_TEST1_MASK    0x20
#define    RTL8367D_ACT_TEST1_OFFSET    4
#define    RTL8367D_ACT_TEST1_MASK    0x10
#define    RTL8367D_PB_TEST1_OFFSET    3
#define    RTL8367D_PB_TEST1_MASK    0x8
#define    RTL8367D_OUTQ_TEST1_OFFSET    2
#define    RTL8367D_OUTQ_TEST1_MASK    0x4
#define    RTL8367D_L2_TEST1_OFFSET    1
#define    RTL8367D_L2_TEST1_MASK    0x2

#define    RTL8367D_REG_BIST_CFG_TCAM    0x671f
#define    RTL8367D_TCAM_WATS_OFFSET    12
#define    RTL8367D_TCAM_WATS_MASK    0x3000
#define    RTL8367D_TCAM_WAS_OFFSET    9
#define    RTL8367D_TCAM_WAS_MASK    0xE00
#define    RTL8367D_TCAM_WAEN_OFFSET    8
#define    RTL8367D_TCAM_WAEN_MASK    0x100
#define    RTL8367D_TCAM_TM_OFFSET    7
#define    RTL8367D_TCAM_TM_MASK    0x80
#define    RTL8367D_BIST_CFG_TCAM_TCAM_RDS_OFFSET    3
#define    RTL8367D_BIST_CFG_TCAM_TCAM_RDS_MASK    0x78
#define    RTL8367D_BIST_CFG_TCAM_TCAM_MDS_OFFSET    0
#define    RTL8367D_BIST_CFG_TCAM_TCAM_MDS_MASK    0x7

#define    RTL8367D_REG_BIST_RSLT_PAUSE    0x6720
#define    RTL8367D_NCTLRAM_PAUSE_OFFSET    12
#define    RTL8367D_NCTLRAM_PAUSE_MASK    0x1000
#define    RTL8367D_IROM_PAUSE_OFFSET    11
#define    RTL8367D_IROM_PAUSE_MASK    0x800
#define    RTL8367D_IRAM_PAUSE_OFFSET    10
#define    RTL8367D_IRAM_PAUSE_MASK    0x400
#define    RTL8367D_ERAM_PAUSE_OFFSET    9
#define    RTL8367D_ERAM_PAUSE_MASK    0x200
#define    RTL8367D_HSACTRL_PAUSE_OFFSET    8
#define    RTL8367D_HSACTRL_PAUSE_MASK    0x100
#define    RTL8367D_CVLAN_PAUSE_OFFSET    7
#define    RTL8367D_CVLAN_PAUSE_MASK    0x80
#define    RTL8367D_MIB_PAUSE_OFFSET    6
#define    RTL8367D_MIB_PAUSE_MASK    0x40
#define    RTL8367D_HT_PAUSE_OFFSET    5
#define    RTL8367D_HT_PAUSE_MASK    0x20
#define    RTL8367D_ACT_PAUSE_OFFSET    4
#define    RTL8367D_ACT_PAUSE_MASK    0x10
#define    RTL8367D_PB_PAUSE_OFFSET    3
#define    RTL8367D_PB_PAUSE_MASK    0x8
#define    RTL8367D_OUTQ_PAUSE_OFFSET    2
#define    RTL8367D_OUTQ_PAUSE_MASK    0x4
#define    RTL8367D_L2_PAUSE_OFFSET    1
#define    RTL8367D_L2_PAUSE_MASK    0x2
#define    RTL8367D_TCAM_PAUSE_OFFSET    0
#define    RTL8367D_TCAM_PAUSE_MASK    0x1

#define    RTL8367D_REG_BIST_RSLT_DONE    0x6721
#define    RTL8367D_NCTLROM_DONE_OFFSET    13
#define    RTL8367D_NCTLROM_DONE_MASK    0x2000
#define    RTL8367D_NCTLRAM_DONE_OFFSET    12
#define    RTL8367D_NCTLRAM_DONE_MASK    0x1000
#define    RTL8367D_IROM_DONE_OFFSET    11
#define    RTL8367D_IROM_DONE_MASK    0x800
#define    RTL8367D_IRAM_DONE_OFFSET    10
#define    RTL8367D_IRAM_DONE_MASK    0x400
#define    RTL8367D_ERAM_DONE_OFFSET    9
#define    RTL8367D_ERAM_DONE_MASK    0x200
#define    RTL8367D_HSACTRL_DONE_OFFSET    8
#define    RTL8367D_HSACTRL_DONE_MASK    0x100
#define    RTL8367D_CVLAN_DONE_OFFSET    7
#define    RTL8367D_CVLAN_DONE_MASK    0x80
#define    RTL8367D_MIB_DONE_OFFSET    6
#define    RTL8367D_MIB_DONE_MASK    0x40
#define    RTL8367D_HT_DONE_OFFSET    5
#define    RTL8367D_HT_DONE_MASK    0x20
#define    RTL8367D_ACT_DONE_OFFSET    4
#define    RTL8367D_ACT_DONE_MASK    0x10
#define    RTL8367D_PB_DONE_OFFSET    3
#define    RTL8367D_PB_DONE_MASK    0x8
#define    RTL8367D_OUTQ_DONE_OFFSET    2
#define    RTL8367D_OUTQ_DONE_MASK    0x4
#define    RTL8367D_L2_DONE_OFFSET    1
#define    RTL8367D_L2_DONE_MASK    0x2
#define    RTL8367D_TCAM_DONE_OFFSET    0
#define    RTL8367D_TCAM_DONE_MASK    0x1

#define    RTL8367D_REG_BIST_RSLT_DRF_DONE    0x6722
#define    RTL8367D_NCTLRAM_DRF_DONE_OFFSET    12
#define    RTL8367D_NCTLRAM_DRF_DONE_MASK    0x1000
#define    RTL8367D_IROM_DRF_DONE_OFFSET    11
#define    RTL8367D_IROM_DRF_DONE_MASK    0x800
#define    RTL8367D_IRAM_DRF_DONE_OFFSET    10
#define    RTL8367D_IRAM_DRF_DONE_MASK    0x400
#define    RTL8367D_ERAM_DRF_DONE_OFFSET    9
#define    RTL8367D_ERAM_DRF_DONE_MASK    0x200
#define    RTL8367D_HSACTRL_DRF_DONE_OFFSET    8
#define    RTL8367D_HSACTRL_DRF_DONE_MASK    0x100
#define    RTL8367D_CVLAN_DRF_DONE_OFFSET    7
#define    RTL8367D_CVLAN_DRF_DONE_MASK    0x80
#define    RTL8367D_MIB_DRF_DONE_OFFSET    6
#define    RTL8367D_MIB_DRF_DONE_MASK    0x40
#define    RTL8367D_HT_DRF_DONE_OFFSET    5
#define    RTL8367D_HT_DRF_DONE_MASK    0x20
#define    RTL8367D_ACT_DRF_DONE_OFFSET    4
#define    RTL8367D_ACT_DRF_DONE_MASK    0x10
#define    RTL8367D_PB_DRF_DONE_OFFSET    3
#define    RTL8367D_PB_DRF_DONE_MASK    0x8
#define    RTL8367D_OUTQ_DRF_DONE_OFFSET    2
#define    RTL8367D_OUTQ_DRF_DONE_MASK    0x4
#define    RTL8367D_L2_DRF_DONE_OFFSET    1
#define    RTL8367D_L2_DRF_DONE_MASK    0x2
#define    RTL8367D_TCAM_DRF_DONE_OFFSET    0
#define    RTL8367D_TCAM_DRF_DONE_MASK    0x1

#define    RTL8367D_REG_BIST_RSLT_FAIL    0x6723
#define    RTL8367D_NCTLROM_FAIL_OFFSET    13
#define    RTL8367D_NCTLROM_FAIL_MASK    0x2000
#define    RTL8367D_NCTLRAM_FAIL_OFFSET    12
#define    RTL8367D_NCTLRAM_FAIL_MASK    0x1000
#define    RTL8367D_IROM_FAIL_OFFSET    11
#define    RTL8367D_IROM_FAIL_MASK    0x800
#define    RTL8367D_IRAM_FAIL_OFFSET    10
#define    RTL8367D_IRAM_FAIL_MASK    0x400
#define    RTL8367D_ERAM_FAIL_OFFSET    9
#define    RTL8367D_ERAM_FAIL_MASK    0x200
#define    RTL8367D_HSACTRL_FAIL_OFFSET    8
#define    RTL8367D_HSACTRL_FAIL_MASK    0x100
#define    RTL8367D_CVLAN_FAIL_OFFSET    7
#define    RTL8367D_CVLAN_FAIL_MASK    0x80
#define    RTL8367D_MIB_FAIL_OFFSET    6
#define    RTL8367D_MIB_FAIL_MASK    0x40
#define    RTL8367D_HT_FAIL_OFFSET    5
#define    RTL8367D_HT_FAIL_MASK    0x20
#define    RTL8367D_ACT_FAIL_OFFSET    4
#define    RTL8367D_ACT_FAIL_MASK    0x10
#define    RTL8367D_BIST_RSLT_FAIL_PB_FAIL_OFFSET    3
#define    RTL8367D_BIST_RSLT_FAIL_PB_FAIL_MASK    0x8
#define    RTL8367D_BIST_RSLT_FAIL_OUTQ_FAIL_OFFSET    2
#define    RTL8367D_BIST_RSLT_FAIL_OUTQ_FAIL_MASK    0x4
#define    RTL8367D_BIST_RSLT_FAIL_L2_FAIL_OFFSET    1
#define    RTL8367D_BIST_RSLT_FAIL_L2_FAIL_MASK    0x2
#define    RTL8367D_TCAM_FAIL_OFFSET    0
#define    RTL8367D_TCAM_FAIL_MASK    0x1

#define    RTL8367D_REG_BIST_RSLT_DRF_FAIL    0x6724
#define    RTL8367D_NCTLRAM_DRF_FAIL_OFFSET    12
#define    RTL8367D_NCTLRAM_DRF_FAIL_MASK    0x1000
#define    RTL8367D_IROM_DRF_FAIL_OFFSET    11
#define    RTL8367D_IROM_DRF_FAIL_MASK    0x800
#define    RTL8367D_IRAM_DRF_FAIL_OFFSET    10
#define    RTL8367D_IRAM_DRF_FAIL_MASK    0x400
#define    RTL8367D_ERAM_DRF_FAIL_OFFSET    9
#define    RTL8367D_ERAM_DRF_FAIL_MASK    0x200
#define    RTL8367D_HSACTRL_DRF_FAIL_OFFSET    8
#define    RTL8367D_HSACTRL_DRF_FAIL_MASK    0x100
#define    RTL8367D_CVLAN_DRF_FAIL_OFFSET    7
#define    RTL8367D_CVLAN_DRF_FAIL_MASK    0x80
#define    RTL8367D_MIB_DRF_FAIL_OFFSET    6
#define    RTL8367D_MIB_DRF_FAIL_MASK    0x40
#define    RTL8367D_HT_DRF_FAIL_OFFSET    5
#define    RTL8367D_HT_DRF_FAIL_MASK    0x20
#define    RTL8367D_ACT_DRF_FAIL_OFFSET    4
#define    RTL8367D_ACT_DRF_FAIL_MASK    0x10
#define    RTL8367D_BIST_RSLT_DRF_FAIL_PB_DRF_FAIL_OFFSET    3
#define    RTL8367D_BIST_RSLT_DRF_FAIL_PB_DRF_FAIL_MASK    0x8
#define    RTL8367D_BIST_RSLT_DRF_FAIL_OUTQ_DRF_FAIL_OFFSET    2
#define    RTL8367D_BIST_RSLT_DRF_FAIL_OUTQ_DRF_FAIL_MASK    0x4
#define    RTL8367D_BIST_RSLT_DRF_FAIL_L2_DRF_FAIL_OFFSET    1
#define    RTL8367D_BIST_RSLT_DRF_FAIL_L2_DRF_FAIL_MASK    0x2
#define    RTL8367D_TCAM_DRF_FAIL_OFFSET    0
#define    RTL8367D_TCAM_DRF_FAIL_MASK    0x1


#endif /*#ifndef _RTL8367D_REG_H_*/

